专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07727892B2 Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects 有权
标题翻译：用于形成用于集成电路互连的金属 - 金属氧化物蚀刻停止/屏障的方法和装置
公开(公告)号：US07727892B2
公开(公告)日：2010-06-01
申请号：US10255930
申请日：2002-09-25
申请人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
发明人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
IPC分类号： H01L21/311
CPC分类号： H01L21/76849 , H01L21/76829 , H01L21/76834 , H01L21/76855 , H01L21/76888 , H01L21/76897 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.
摘要翻译：描述了用于与金属 - 金属氧化物电迁移屏障和蚀刻停止形成互连的方法和装置。在本发明的一个实施例中，该方法包括在平坦化的互连层的顶部上沉积金属层，所述互连层具有层间电介质（ILD），其顶部与导电互连的顶部是平面的。在本发明的一个实施方案中，该方法包括使金属层与ILD反应以在ILD的顶部形成金属氧化物层。同时，金属层不会被导电互连显着地氧化，从而在导电互连上形成金属阻挡层以改善电迁移性能。金属屏障和金属氧化物层一起包括保护层。随后可以在保护层上形成第二ILD，并且保护层可以在随后的第二ILD蚀刻期间进行蚀刻停止。

2. 发明授权

US5430595A Electrostatic discharge protection circuit 失效
标题翻译：静电放电保护电路
公开(公告)号：US5430595A
公开(公告)日：1995-07-04
申请号：US138472
申请日：1993-10-15
申请人： Glen R. Wagner , Jeffrey Smith , Jose A. Maiz , Clair C. Webb , William M. Holt
发明人： Glen R. Wagner , Jeffrey Smith , Jose A. Maiz , Clair C. Webb , William M. Holt
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06 , H01L29/861 , H02H9/04 , H02H3/22
CPC分类号： H01L27/0262 , H01L27/0251
摘要： A device for protecting an integrated circuit (IC) against electrostatic discharge (ESD) includes a self-triggered silicon controlled rectifier (STSCR) coupled across the internal supply potentials of the integrated circuit. The STSCR exhibits a snap-back in its current versus voltage characteristic which is triggered at a predetermined voltage during an ESD event. As large voltages build up across the chip capacitance, the predetermined voltage of the SCR is triggered at a potential which is sufficiently low to protect the internal junctions of the IC from destructive reverse breakdown. The STSCR comprises a pnpn semiconductor structure which includes a n-well disposed in a p-substrate. A first n+ region and a p-type region are both disposed in the n-well. The n+ and p-type regions are spaced apart and electrically connected to form the anode of the SCR. The ESD protection device also includes diode clamps between the periphery and internal power supply lines, and a novel well resistor which provides a distributed resistance further protecting sensitive output buffer circuitry.
摘要翻译：用于保护集成电路（IC）防止静电放电（ESD）的装置包括耦合在集成电路的内部电源上的自触发可控硅整流器（STSCR）。 STSCR呈现其在ESD事件期间以预定电压触发的电流对电压特性的瞬时恢复。当跨越芯片电容的大电压积聚时，SCR的预定电压以足够低的电位被触发，以保护IC的内部结不受破坏性的反向击穿。 STSCR包括pnpn半导体结构，其包括设置在p衬底中的n阱。第n +区和p型区均设置在n阱中。 n +和p型区域间隔开并电连接以形成SCR的阳极。 ESD保护器件还包括在外围电源线和内部电源线之间的二极管钳位，以及提供进一步保护敏感输出缓冲器电路的分布电阻的新型阱电阻器。

3. 发明授权

US08299617B2 Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects 有权
标题翻译：用于形成用于集成电路互连的金属 - 金属氧化物蚀刻停止/屏障的方法和装置
公开(公告)号：US08299617B2
公开(公告)日：2012-10-30
申请号：US12763038
申请日：2010-04-19
申请人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
发明人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
IPC分类号： H01L29/40
CPC分类号： H01L21/76849 , H01L21/76829 , H01L21/76834 , H01L21/76855 , H01L21/76888 , H01L21/76897 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.
摘要翻译：描述了用于与金属 - 金属氧化物电迁移屏障和蚀刻停止形成互连的方法和装置。在本发明的一个实施例中，该方法包括在平坦化的互连层的顶部上沉积金属层，所述互连层具有层间电介质（ILD），其顶部与导电互连的顶部是平面的。在本发明的一个实施方案中，该方法包括使金属层与ILD反应以在ILD的顶部形成金属氧化物层。同时，金属层不会被导电互连显着地氧化，从而在导电互连上形成金属阻挡层以改善电迁移性能。金属屏障和金属氧化物层一起包括保护层。随后可以在保护层上形成第二ILD，并且保护层可以在随后的第二ILD蚀刻期间进行蚀刻停止。

4. 发明申请

US20100219529A1 METHOD AND APPARATUS FOR FORMING METAL-METAL OXIDE ETCH STOP/BARRIER FOR INTEGRATED CIRCUIT INTERCONNECTS 有权
标题翻译：用于形成用于集成电路互连的金属氧化物蚀刻停止/障碍物的方法和装置
公开(公告)号：US20100219529A1
公开(公告)日：2010-09-02
申请号：US12763038
申请日：2010-04-19
申请人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
发明人： Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
IPC分类号： H01L23/532
CPC分类号： H01L21/76849 , H01L21/76829 , H01L21/76834 , H01L21/76855 , H01L21/76888 , H01L21/76897 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.
摘要翻译：描述了用于与金属 - 金属氧化物电迁移屏障和蚀刻停止形成互连的方法和装置。在本发明的一个实施例中，该方法包括在平坦化的互连层的顶部上沉积金属层，所述互连层具有层间电介质（ILD），其顶部与导电互连的顶部是平面的。在本发明的一个实施方案中，该方法包括使金属层与ILD反应以在ILD的顶部形成金属氧化物层。同时，金属层不会被导电互连显着地氧化，从而在导电互连上形成金属阻挡层以改善电迁移性能。金属屏障和金属氧化物层一起包括保护层。随后可以在保护层上形成第二ILD，并且保护层可以在随后的第二ILD蚀刻期间进行蚀刻停止。

5. 发明申请

US20100070809A1 REPAIR BITS FOR A LOW VOLTAGE CACHE 有权
标题翻译：维修低电压缓存的位置
公开(公告)号：US20100070809A1
公开(公告)日：2010-03-18
申请号：US12623169
申请日：2009-11-20
申请人： Morgan J. Dempsey , Jose A. Maiz
发明人： Morgan J. Dempsey , Jose A. Maiz
IPC分类号： G11C29/00 , G06F11/16
CPC分类号： G11C29/808 , G11C15/00
摘要： A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.
摘要翻译：本文描述了用于修复高速缓冲存储器/阵列的方法和装置。缓存包括多个行，并且可以在列中逻辑地查看。耦合到高速缓存的修复缓存包括映射到每个逻辑可见列的修复位。修复模块基于任何个体或因素组合来确定在列内修复的坏位，例如每个高速缓存行的错误数量，由于错误校正码每行高速缓存可纠错的数量（ ECC），位的故障率或其他考虑。在访问包括坏位的高速缓存行时，坏位被映射到包括坏位的列的修复位透明地修复。

6. 发明授权

US07679145B2 Transistor performance enhancement using engineered strains 失效
标题翻译：使用工程菌株的晶体管性能提升
公开(公告)号：US07679145B2
公开(公告)日：2010-03-16
申请号：US10930247
申请日：2004-08-31
申请人： Jun He , Zhiyong Ma , Jose A. Maiz , Mark Bohr , Martin D. Giles , Guanghai Xu
发明人： Jun He , Zhiyong Ma , Jose A. Maiz , Mark Bohr , Martin D. Giles , Guanghai Xu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L23/495 , H01L23/34
CPC分类号： H01L29/7842 , H01L21/823807 , H01L23/42 , H01L2224/16 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01087 , H01L2924/01322 , H01L2924/10253 , H01L2924/15311 , H01L2924/16152 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the performance of at least a portion of the MOS devices on the die.
摘要翻译：具有诸如集成电路管芯的金属氧化物半导体（MOS）器件的半导体衬底被机械耦合到应力结构，以施加提高模具上的至少一部分MOS器件的性能的应力。

7. 发明授权

US07647536B2 Repair bits for a low voltage cache 有权
标题翻译：修复低电压缓存的位
公开(公告)号：US07647536B2
公开(公告)日：2010-01-12
申请号：US11322988
申请日：2005-12-30
申请人： Morgan J. Dempsey , Jose A. Maiz
发明人： Morgan J. Dempsey , Jose A. Maiz
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C15/00
摘要： A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.
摘要翻译：本文描述了用于修复高速缓冲存储器/阵列的方法和装置。缓存包括多个行，并且可以在列中逻辑地查看。耦合到高速缓存的修复缓存包括映射到每个逻辑可见列的修复位。修复模块基于任何个体或因素组合来确定在列内修复的坏位，例如每个高速缓存行的错误数量，由于错误校正码每行高速缓存可纠错的数量（ ECC），位的故障率或其他考虑。在访问包括坏位的高速缓存行时，坏位被映射到包括坏位的列的修复位透明地修复。

8. 发明授权

US07662674B2 Methods of forming electromigration and thermal gradient based fuse structures 有权
标题翻译：形成电迁移和基于热梯度的熔丝结构的方法
公开(公告)号：US07662674B2
公开(公告)日：2010-02-16
申请号：US11133835
申请日：2005-05-20
申请人： Jose A. Maiz , Jun He , Mark Bohr
发明人： Jose A. Maiz , Jun He , Mark Bohr
IPC分类号： H01L21/82 , H01L21/336
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括通过在第一互连结构上形成至少一个通孔来形成金属熔丝结构，将所述至少一个通孔与阻挡层衬里，然后在所述至少一个通孔上形成第二互连结构。

9. 发明授权

US06794755B2 Surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement 有权
标题翻译：用于电迁移和粘附改善的集成电路中金属互连的表面改变
公开(公告)号：US06794755B2
公开(公告)日：2004-09-21
申请号：US10400128
申请日：2003-03-25
申请人： Jose A. Maiz , Xiaorong Morrow , Thomas Marieb , Carolyn Block , Jihperng Leu , Paul McGregor , Markus Kuhn , Mitchell C. Taylor
发明人： Jose A. Maiz , Xiaorong Morrow , Thomas Marieb , Carolyn Block , Jihperng Leu , Paul McGregor , Markus Kuhn , Mitchell C. Taylor
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/32051 , H01L21/76801 , H01L21/76805 , H01L21/76807 , H01L21/76822 , H01L21/76825 , H01L21/76834 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76858 , H01L21/76864 , H01L21/76867 , H01L21/76886 , H01L21/76888 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Described is a method and apparatus for altering the top surface of a metal interconnect. In one embodiment of the invention, a metal interconnect and a barrier layer are formed into an interlayer dielectric (ILD) and the metal interconnect and the barrier layer are planarized to the top of the ILD. The top surfaces of the metal interconnect, the barrier layer, and the ILD are altered with a second metal to form an electromigration barrier. In one embodiment of the invention, the second metal is prevented from contaminating the electrical resistivity of the metal interconnect.
摘要翻译：描述了用于改变金属互连的顶表面的方法和装置。在本发明的一个实施例中，将金属互连和阻挡层形成为层间电介质（ILD），并将金属互连和阻挡层平面化到ILD的顶部。金属互连，阻挡层和ILD的顶表面用第二金属改变以形成电迁移屏障。在本发明的一个实施例中，防止了第二金属污染金属互连的电阻率。

10. 发明申请

US20140237213A1 HIGH DOSE RADIATION DETECTOR 有权
标题翻译：高剂量辐射检测器
公开(公告)号：US20140237213A1
公开(公告)日：2014-08-21
申请号：US13772260
申请日：2013-02-20
申请人： Balkaran Singh GILL , Norbert R. SEIFERT , Jose A. MAIZ , Xiaofeng YANG , Avner KORNFELD
发明人： Balkaran Singh GILL , Norbert R. SEIFERT , Jose A. MAIZ , Xiaofeng YANG , Avner KORNFELD
IPC分类号： G06F9/22
CPC分类号： G06F9/22 , G01T1/026 , G06F11/183 , G06F11/3006 , G06F11/3024 , G06F11/3058 , G06F11/3093
摘要： Described is a processor comprising: a plurality of radiation detectors; a first logic unit to receive outputs from the plurality of radiation detectors, the logic unit to generate an output according to the received outputs, the output of the first logic unit indicating whether the processor was exposed to incoming radiations; and a second logic unit to receive the output from the first logic unit, and to cause the processor to perform an action according to the output from the first logic unit.
摘要翻译：描述了一种处理器，包括：多个辐射检测器; 第一逻辑单元，用于接收来自所述多个辐射检测器的输出，所述逻辑单元根据所接收的输出生成输出，所述第一逻辑单元的输出指示所述处理器是否暴露于进入的辐射; 以及第二逻辑单元，用于接收来自第一逻辑单元的输出，并且使得处理器根据来自第一逻辑单元的输出执行动作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式