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1. 发明授权

US5430595A Electrostatic discharge protection circuit 失效
标题翻译：静电放电保护电路
公开(公告)号：US5430595A
公开(公告)日：1995-07-04
申请号：US138472
申请日：1993-10-15
申请人： Glen R. Wagner , Jeffrey Smith , Jose A. Maiz , Clair C. Webb , William M. Holt
发明人： Glen R. Wagner , Jeffrey Smith , Jose A. Maiz , Clair C. Webb , William M. Holt
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06 , H01L29/861 , H02H9/04 , H02H3/22
CPC分类号： H01L27/0262 , H01L27/0251
摘要： A device for protecting an integrated circuit (IC) against electrostatic discharge (ESD) includes a self-triggered silicon controlled rectifier (STSCR) coupled across the internal supply potentials of the integrated circuit. The STSCR exhibits a snap-back in its current versus voltage characteristic which is triggered at a predetermined voltage during an ESD event. As large voltages build up across the chip capacitance, the predetermined voltage of the SCR is triggered at a potential which is sufficiently low to protect the internal junctions of the IC from destructive reverse breakdown. The STSCR comprises a pnpn semiconductor structure which includes a n-well disposed in a p-substrate. A first n+ region and a p-type region are both disposed in the n-well. The n+ and p-type regions are spaced apart and electrically connected to form the anode of the SCR. The ESD protection device also includes diode clamps between the periphery and internal power supply lines, and a novel well resistor which provides a distributed resistance further protecting sensitive output buffer circuitry.
摘要翻译：用于保护集成电路（IC）防止静电放电（ESD）的装置包括耦合在集成电路的内部电源上的自触发可控硅整流器（STSCR）。 STSCR呈现其在ESD事件期间以预定电压触发的电流对电压特性的瞬时恢复。当跨越芯片电容的大电压积聚时，SCR的预定电压以足够低的电位被触发，以保护IC的内部结不受破坏性的反向击穿。 STSCR包括pnpn半导体结构，其包括设置在p衬底中的n阱。第n +区和p型区均设置在n阱中。 n +和p型区域间隔开并电连接以形成SCR的阳极。 ESD保护器件还包括在外围电源线和内部电源线之间的二极管钳位，以及提供进一步保护敏感输出缓冲器电路的分布电阻的新型阱电阻器。

2. 发明授权

US5293603A Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path 失效
标题翻译：用于基于微处理器的计算机系统的缓存子系统，具有同步和异步数据路径
公开(公告)号：US5293603A
公开(公告)日：1994-03-08
申请号：US710079
申请日：1991-06-04
申请人： Peter D. MacWilliams , Clair C. Webb , Robert L. Farrell
发明人： Peter D. MacWilliams , Clair C. Webb , Robert L. Farrell
IPC分类号： G06F12/08 , G06F13/16
CPC分类号： G06F12/0864 , G06F12/0804 , G06F12/0835 , G06F12/0862 , G06F12/0897 , G06F2212/6082
摘要： An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for optimizing burst read and write operations to and from the CPU bus. These circuits allow a full cache line to be read or written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.
摘要翻译：用作缓存子系统的集成电路实现了高速缓存静态随机存取存储器（SRAM）存储阵列，中央处理器单元（CPU）总线接口和主存储器总线接口。 CPU总线和主存储器总线接口包括多路复用器，缓冲器和本地控制，用于优化对CPU总线的突发读和写操作。这些电路允许在SRAM阵列的单个访问中读取或写入完整的高速缓存行。控制逻辑用于CPU总线接口，用于按照CPU定义的顺序控制CPU脉冲串。存储器总线接口包括用于执行存储器总线读取，写入，回写和监听的内部缓冲器。跟踪逻辑用于确定要用于特定存储器总线周期的适当的内部缓冲器。另外，包括数据路径，用于在CPU和存储器总线接口之间透明地传递数据，而不会对SRAM阵列造成干扰。

3. 发明授权

US5228134A Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus 失效
标题翻译：与同步中央处理器总线和异步存储器总线一起使用的高速缓存存储器集成电路
公开(公告)号：US5228134A
公开(公告)日：1993-07-13
申请号：US710075
申请日：1991-06-04
申请人： Peter D. MacWilliams , Clair C. Webb , Robert L. Farrell
发明人： Peter D. MacWilliams , Clair C. Webb , Robert L. Farrell
IPC分类号： G06F12/08 , G11C11/401
CPC分类号： G06F12/0879
摘要： An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface incorporating multiplexers and buffers circuits for optimizing burst read and write operations across the CPU bus. Theses circuits allow a full cache line to be read/written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.
摘要翻译：集成电路实现了高速缓存静态随机存取存储器（SRAM）存储元件，其包括集成有多路复用器和缓冲器电路的中央处理器单元（CPU）总线接口，用于优化跨CPU总线的突发读和写操作。这些电路允许在SRAM阵列的单个访问中读取/写入完整的高速缓存行。控制逻辑用于CPU总线接口，用于按照CPU定义的顺序控制CPU脉冲串。存储器总线接口包括用于执行存储器总线读取，写入，回写和监听的内部缓冲器。跟踪逻辑用于确定要用于特定存储器总线周期的适当的内部缓冲器。另外，包括数据路径，用于在CPU和存储器总线接口之间透明地传递数据，而不会对SRAM阵列造成干扰。

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