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1. 发明授权

US08505970B2 Airbag cushion for vehicles 有权
标题翻译：汽车安全气垫
公开(公告)号：US08505970B2
公开(公告)日：2013-08-13
申请号：US13316537
申请日：2011-12-11
申请人： Eung Man Kim , Taeg Young Ahn , Hak Muk Park , Jong Hyuk Kim
发明人： Eung Man Kim , Taeg Young Ahn , Hak Muk Park , Jong Hyuk Kim
IPC分类号： B60R21/16
CPC分类号： B60R21/2338 , B60R21/205 , B60R21/239 , B60R2021/23384
摘要： An airbag cushion for vehicles includes a cushion body, vent holes, tubes and a tether. The vent holes are formed in the cushion body at opposite positions. The tubes are connected to the respective vent holes. The tubes are deployed out of the vent holes by deployment of the cushion body so that gas is discharged out of the cushion body through the tubes. The tether connects the tubes to each other and is severed when pressure in the cushion body reaches a predetermined degree. At the point of time at which the weight of the occupant is applied to the airbag cushion, the pressure in the airbag cushion is released, thus reducing the risk of the deployment of the airbag cushion injuring the occupant.
摘要翻译：用于车辆的气囊垫包括缓冲体，排气孔，管和系绳。通气孔在相对位置的缓冲体中形成。管连接到相应的通气孔。通过展开衬垫体将管部署在排气孔之外，使得气体通过管排出衬垫体。系绳将管彼此连接，当缓冲体中的压力达到预定的程度时被切断。在将乘员的重量施加到气囊垫的时间点处，气囊缓冲器中的压力被释放，从而降低了安全气囊缓冲部件的受伤危险。

2. 发明授权

US08405158B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08405158B2
公开(公告)日：2013-03-26
申请号：US12832373
申请日：2010-07-08
申请人： Young-Bae Yoon , Jong-Hyuk Kim , Keonsoo Kim , Youngseop Rah , Yoonmoon Park
发明人： Young-Bae Yoon , Jong-Hyuk Kim , Keonsoo Kim , Youngseop Rah , Yoonmoon Park
IPC分类号： H01L27/088 , H01L29/76
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/11519
摘要： A semiconductor memory device and method of manufacturing the same, the device including string structures, the string structures including two or more adjacent string selection transistors connected in series to each other in a first direction and being spaced apart from one another in a second direction intersecting the first direction, the two or more string selection transistors having different threshold voltages; string selection lines, the string selection lines connecting the adjacent string selection transistors of the string structures in the second direction; and a bit line electrically connecting two or more adjacent string structures, wherein a device isolation layer between the adjacent string selection transistors in the second direction has recessed regions, and profiles of the recessed regions on respective sides of the string selection transistors are different from each other.
摘要翻译：一种半导体存储器件及其制造方法，该器件包括串联结构，串联结构包括两个或多个相邻的串选择晶体管，它们在第一方向上彼此串联连接，并且在第二方向上相互间隔开所述第一方向，所述两个或更多个串选择晶体管具有不同的阈值电压; 串选择线，串串选择线，连接串结构的相邻串选择晶体管沿第二方向; 以及电连接两个或更多个相邻串结构的位线，其中在第二方向上的相邻串选择晶体管之间的器件隔离层具有凹陷区域，并且串选择晶体管的相应侧上的凹陷区域的轮廓与每个不同其他。

3. 发明申请

US20130062870A1 AIRBAG CUSHION FOR VEHICLES 有权
标题翻译：汽车安全气囊
公开(公告)号：US20130062870A1
公开(公告)日：2013-03-14
申请号：US13316537
申请日：2011-12-11
申请人： Eung Man Kim , Taeg Young Ahn , Hak Muk Park , Jong Hyuk Kim
发明人： Eung Man Kim , Taeg Young Ahn , Hak Muk Park , Jong Hyuk Kim
IPC分类号： B60R21/16
CPC分类号： B60R21/2338 , B60R21/205 , B60R21/239 , B60R2021/23384
摘要： An airbag cushion for vehicles includes a cushion body, vent holes, tubes and a tether. The vent holes are formed in the cushion body at opposite positions. The tubes are connected to the respective vent holes. The tubes are deployed out of the vent holes by deployment of the cushion body so that gas is discharged out of the cushion body through the tubes. The tether connects the tubes to each other and is severed when pressure in the cushion body reaches a predetermined degree. At the point of time at which the weight of the occupant is applied to the airbag cushion, the pressure in the airbag cushion is released, thus reducing the risk of the deployment of the airbag cushion injuring the occupant.
摘要翻译：用于车辆的气囊垫包括缓冲体，排气孔，管和系绳。通气孔在相对位置的缓冲体中形成。管连接到相应的通气孔。通过展开衬垫体将管部署在排气孔之外，使得气体通过管排出衬垫体。系绳将管彼此连接，当缓冲体中的压力达到预定的程度时被切断。在将乘员的重量施加到气囊垫的时间点处，气囊缓冲器中的压力被释放，从而降低了安全气囊缓冲部件的受伤危险。

4. 发明授权

US07998834B2 Substrate level bonding method and substrate level package 有权
标题翻译：基板级接合方法和基板级封装
公开(公告)号：US07998834B2
公开(公告)日：2011-08-16
申请号：US12646691
申请日：2009-12-23
申请人： Chul-Soo Kim , Kuk-Jin Chun , Sung-Chan Kang , Jong-Hyuk Kim , In-Sang Song , Duck-Hwan Kim , Jae-Shik Shin
发明人： Chul-Soo Kim , Kuk-Jin Chun , Sung-Chan Kang , Jong-Hyuk Kim , In-Sang Song , Duck-Hwan Kim , Jae-Shik Shin
IPC分类号： H01L21/30 , H01L21/00
CPC分类号： H01L23/10 , H01L21/50 , H01L21/76898 , H01L25/50 , H01L27/14601 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are a substrate level bonding method and a substrate level package formed thereby. The substrate level package includes a plurality of unit substrate sections, a base substrate, and a plurality of substrate adhesion sections. The unit substrate sections are separated from each other by holes. The base substrate is disposed to face the unit substrate sections. The substrate adhesion sections are interposed between the unit substrate sections and the base substrate to bond the unit substrate sections to the base substrate and which are formed of DFR material, whose at least one portion is uncured.
摘要翻译：公开了一种由此形成的衬底水平焊接方法和衬底层封装。基板级封装包括多个单元基板部分，基底基板和多个基板粘合部分。单元基板部分通过孔彼此分离。基底基板设置成面对单元基板部分。基板粘合部分插入在单元基板部分和基底基板之间，以将单元基板部分粘合到基底基板上，并且由至少一部分未固化的DFR材料形成。

5. 发明申请

US20110038211A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110038211A1
公开(公告)日：2011-02-17
申请号：US12832373
申请日：2010-07-08
申请人： Young-Bae Yoon , Jong-Hyuk Kim , Keonsoo Kim , Youngseop Rah , Yoonmoon Park
发明人： Young-Bae Yoon , Jong-Hyuk Kim , Keonsoo Kim , Youngseop Rah , Yoonmoon Park
IPC分类号： G11C16/04 , H01L27/088
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/11519
摘要： A semiconductor memory device and method of manufacturing the same, the device including string structures, the string structures including two or more adjacent string selection transistors connected in series to each other in a first direction and being spaced apart from one another in a second direction intersecting the first direction, the two or more string selection transistors having different threshold voltages; string selection lines, the string selection lines connecting the adjacent string selection transistors of the string structures in the second direction; and a bit line electrically connecting two or more adjacent string structures, wherein a device isolation layer between the adjacent string selection transistors in the second direction has recessed regions, and profiles of the recessed regions on respective sides of the string selection transistors are different from each other.
摘要翻译：一种半导体存储器件及其制造方法，该器件包括串联结构，串联结构包括两个或更多个相邻的串选择晶体管，它们在第一方向上彼此串联连接并且沿第二方向相互间隔开所述第一方向，所述两个或更多个串选择晶体管具有不同的阈值电压; 串选择线，串串选择线，连接串结构的相邻串选择晶体管沿第二方向; 以及电连接两个或更多个相邻串结构的位线，其中在第二方向上的相邻串选择晶体管之间的器件隔离层具有凹陷区域，并且串选择晶体管的相应侧上的凹陷区域的轮廓与每个不同其他。

6. 发明授权

US07709323B2 Methods of forming nand-type nonvolatile memory devices 有权
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US07709323B2
公开(公告)日：2010-05-04
申请号：US12474896
申请日：2009-05-29
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.
摘要翻译：形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层半导体衬底的整个表面使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

7. 发明授权

US07683404B2 Stacked memory and method for forming the same 有权
标题翻译：堆积记忆及其形成方法
公开(公告)号：US07683404B2
公开(公告)日：2010-03-23
申请号：US11709234
申请日：2007-02-22
申请人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Hoo-Sung Cho , Jong-Hyuk Kim
发明人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Hoo-Sung Cho , Jong-Hyuk Kim
IPC分类号： H01L25/065
CPC分类号： H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.
摘要翻译：堆叠存储器包括至少两个半导体层，每个半导体层包括存储单元阵列。晶体管形成在至少两个半导体层的最上半导体层的外围电路区域中。晶体管用于操作存储单元阵列。

8. 发明授权

US07417286B2 Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same 有权
标题翻译：具有单晶薄膜晶体管的半导体集成电路器件及其制造方法
公开(公告)号：US07417286B2
公开(公告)日：2008-08-26
申请号：US11280045
申请日：2005-11-15
申请人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Jong-Hyuk Kim , Kun-Ho Kwak , Hoon Lim
发明人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Jong-Hyuk Kim , Kun-Ho Kwak , Hoon Lim
IPC分类号： H01L23/62
CPC分类号： H01L27/0688 , H01L21/8221
摘要： Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same are provided. The semiconductor integrated circuit devices include an interlayer insulating layer formed on a semiconductor substrate and a single crystalline semiconductor plug penetrating the interlayer insulating layer. A single crystalline semiconductor body pattern is provided on the interlayer insulating layer. The single crystalline semiconductor body pattern has an elevated region and contacts the single crystalline semiconductor plug. The method of forming the single crystalline semiconductor body pattern having the elevated region includes forming a sacrificial layer pattern covering the single crystalline semiconductor plug on the interlayer insulating layer. A capping layer is formed to cover the sacrificial layer pattern and the interlayer insulating layer, and the capping layer is patterned to form an opening which exposes a portion of the sacrificial layer pattern. Subsequently, the sacrificial layer pattern is selectively removed to form a cavity in the capping layer, and a planarized single crystalline semiconductor body pattern is formed to fill the cavity and the opening.
摘要翻译：提供具有单晶薄膜晶体管的半导体集成电路器件及其制造方法。半导体集成电路器件包括形成在半导体衬底上的层间绝缘层和贯穿层间绝缘层的单晶半导体插件。在层间绝缘层上设置单晶体半导体图案。单晶半导体主体图案具有升高的区域并与单晶半导体插头接触。形成具有升高区域的单晶半导体主体图案的方法包括在层间绝缘层上形成覆盖单晶半导体插塞的牺牲层图案。形成覆盖牺牲层图案和层间绝缘层的覆盖层，并且对覆盖层进行图案化以形成露出牺牲层图案的一部分的开口。随后，选择性地去除牺牲层图案以在封盖层中形成空腔，并且形成平坦化的单晶半导体主体图案以填充空腔和开口。

9. 发明申请

US20070241335A1 METHODS OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUITS USING SELECTIVE EPITAXIAL GROWTH AND PARTIAL PLANARIZATION TECHNIQUES AND SEMICONDUCTOR INTEGRATED CIRCUITS FABRICATED THEREBY 审中-公开
标题翻译：使用选择性外延生长和部分平面化技术制造半导体集成电路的方法和半导体集成电路制造的方法
公开(公告)号：US20070241335A1
公开(公告)日：2007-10-18
申请号：US11766655
申请日：2007-06-21
申请人： Kun-Ho KWAK , Jae-Hoon JANG , Soon-Moon JUNG , Won-Seok CHO , Hoon LIM , Sung-Jin KIM , Byung-Jun HWANG , Jong-Hyuk KIM
发明人： Kun-Ho KWAK , Jae-Hoon JANG , Soon-Moon JUNG , Won-Seok CHO , Hoon LIM , Sung-Jin KIM , Byung-Jun HWANG , Jong-Hyuk KIM
IPC分类号： H01L27/108
CPC分类号： H01L27/1108 , H01L27/11
摘要： Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.
摘要翻译：提供了使用SEG技术制造具有薄膜晶体管的半导体集成电路的方法。所述方法包括在单晶半导体衬底上形成层间绝缘层。单晶半导体插件延伸穿过层间绝缘层，并且单晶外延半导体图案与层间绝缘层上的单晶半导体插头接触。单晶外延半导体图案至少部分地平坦化以在层间绝缘层上形成半导体本体层，并且对半导体本体层进行图案化以形成半导体本体。结果，半导体本体包括单晶外延半导体图案的至少一部分。因此，半导体本体具有优异的单晶结构。还提供了使用这些方法制造的半导体集成电路。

10. 发明授权

US07276421B2 Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby 有权
标题翻译：在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件
公开(公告)号：US07276421B2
公开(公告)日：2007-10-02
申请号：US11197836
申请日：2005-08-05
申请人： Jong-Hyuk Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Sung-Jin Kim , Jae-Joo Shim
发明人： Jong-Hyuk Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Sung-Jin Kim , Jae-Joo Shim
IPC分类号： H01L21/331
CPC分类号： H01L21/8221 , H01L21/28525 , H01L21/76877 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/12 , H01L29/785
摘要： Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer. The single crystal semiconductor pattern is grown by an epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer, or by a solid epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer.
摘要翻译：提供了在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件。所述方法包括在单晶半导体层上形成层间绝缘层。形成单晶半导体插塞以穿透层间绝缘层。使用离子注入技术和退火技术在单晶半导体插头内形成半导体氧化物层。结果，单晶半导体插头被分成下插头和上部单晶半导体插头，半导体氧化物层之间插入其中。也就是说，上单晶半导体插头通过半导体氧化物层与下插塞电绝缘。单晶半导体图案形成为与上单晶半导体插头接触并覆盖层间绝缘层。通过使用上部单晶半导体插塞作为种子层的外延生长技术，或通过使用上部单晶半导体插塞作为种子层的固体外延生长技术，生长单晶半导体图案。

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