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1. 发明授权

US07276421B2 Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby 有权
标题翻译：在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件
公开(公告)号：US07276421B2
公开(公告)日：2007-10-02
申请号：US11197836
申请日：2005-08-05
申请人： Jong-Hyuk Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Sung-Jin Kim , Jae-Joo Shim
发明人： Jong-Hyuk Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Sung-Jin Kim , Jae-Joo Shim
IPC分类号： H01L21/331
CPC分类号： H01L21/8221 , H01L21/28525 , H01L21/76877 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/12 , H01L29/785
摘要： Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer. The single crystal semiconductor pattern is grown by an epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer, or by a solid epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer.
摘要翻译：提供了在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件。所述方法包括在单晶半导体层上形成层间绝缘层。形成单晶半导体插塞以穿透层间绝缘层。使用离子注入技术和退火技术在单晶半导体插头内形成半导体氧化物层。结果，单晶半导体插头被分成下插头和上部单晶半导体插头，半导体氧化物层之间插入其中。也就是说，上单晶半导体插头通过半导体氧化物层与下插塞电绝缘。单晶半导体图案形成为与上单晶半导体插头接触并覆盖层间绝缘层。通过使用上部单晶半导体插塞作为种子层的外延生长技术，或通过使用上部单晶半导体插塞作为种子层的固体外延生长技术，生长单晶半导体图案。

2. 发明申请

US20060097319A1 Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby 有权
标题翻译：在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件
公开(公告)号：US20060097319A1
公开(公告)日：2006-05-11
申请号：US11197836
申请日：2005-08-05
申请人： Jong-Hyuk Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Sung-Jin Kim , Jae-Joo Shim
发明人： Jong-Hyuk Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Sung-Jin Kim , Jae-Joo Shim
IPC分类号： H01L27/01
CPC分类号： H01L21/8221 , H01L21/28525 , H01L21/76877 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/12 , H01L29/785
摘要： Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer. The single crystal semiconductor pattern is grown by an epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer, or by a solid epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer.
摘要翻译：提供了在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件。所述方法包括在单晶半导体层上形成层间绝缘层。形成单晶半导体插塞以穿透层间绝缘层。使用离子注入技术和退火技术在单晶半导体插头内形成半导体氧化物层。结果，单晶半导体插头被分成下插头和上部单晶半导体插头，半导体氧化物层之间插入其中。也就是说，上单晶半导体插头通过半导体氧化物层与下插塞电绝缘。单晶半导体图案形成为与上单晶半导体插头接触并覆盖层间绝缘层。通过使用上部单晶半导体插塞作为种子层的外延生长技术，或通过使用上部单晶半导体插塞作为种子层的固体外延生长技术，生长单晶半导体图案。

3. 发明授权

US07276404B2 Methods of forming SRAM cells having landing pad in contact with upper and lower cell gate patterns 有权
公开(公告)号：US07276404B2
公开(公告)日：2007-10-02
申请号：US11589618
申请日：2006-10-30
申请人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Jong-Hyuk Kim , Jae-Joo Shim
发明人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Jong-Hyuk Kim , Jae-Joo Shim
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1108 , Y10S257/903
摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

4. 发明申请

US20070042554A1 Methods of forming SRAM cells having landing pad in contact with upper and lower cell gate patterns 有权
标题翻译：形成具有与上和下单元栅极图案接触的着陆焊盘的SRAM单元的方法
公开(公告)号：US20070042554A1
公开(公告)日：2007-02-22
申请号：US11589618
申请日：2006-10-30
申请人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Jong-Hyuk Kim , Jae-Joo Shim
发明人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Jong-Hyuk Kim , Jae-Joo Shim
IPC分类号： H01L21/336
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1108 , Y10S257/903
摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.
摘要翻译：提供了具有与上下单元栅极图案接触的接合焊盘的SRAM单元及其形成方法。 SRAM单元和方法消除了由于具有垂直堆叠的上下栅极图案的SRAM单元的结构特性而产生的影响，用于稳定地连接半导体衬底的整个表面上的图案。在电池阵列区域的半导体衬底中形成隔离至少一个下部有源区的隔离层。下部有源区域具有两个较低的单元栅极图案。主体图案与半导体衬底平行设置。形成主体图形以限制在下单元门图案上具有上单元栅极图案的上有源区。着陆垫设置在下单元栅极图案之间。形成节点图案以同时接触上单元格栅图案和下单元栅格图案。

5. 发明授权

US07135746B2 SRAM cells having landing pad in contact with upper and lower cell gate patterns and methods of forming the same 有权
公开(公告)号：US07135746B2
公开(公告)日：2006-11-14
申请号：US11268138
申请日：2005-11-07
申请人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Jong-Hyuk Kim , Jae-Joo Shim
发明人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Jong-Hyuk Kim , Jae-Joo Shim
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1108 , Y10S257/903
摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

6. 发明申请

US20060097328A1 SRAM cells having landing pad in contact with upper and lower cell gate patterns and methods of forming the same 有权
标题翻译：具有与上下单元栅极图案接触的着陆焊盘的SRAM单元及其形成方法
公开(公告)号：US20060097328A1
公开(公告)日：2006-05-11
申请号：US11268138
申请日：2005-11-07
申请人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Jong-Hyuk Kim , Jae-Joo Shim
发明人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Jong-Hyuk Kim , Jae-Joo Shim
IPC分类号： H01L29/76
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1108 , Y10S257/903
摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.
摘要翻译：提供了具有与上下单元栅极图案接触的接合焊盘的SRAM单元及其形成方法。 SRAM单元和该方法消除了具有垂直堆叠的上和下栅极图案的SRAM单元的结构特性所产生的影响，用于稳定地连接半导体衬底的整个表面上的图案。在电池阵列区域的半导体衬底中形成隔离至少一个下部有源区的隔离层。下部有源区域具有两个较低的单元栅极图案。主体图案与半导体衬底平行设置。形成主体图形以限制在下单元门图案上具有上单元栅极图案的上有源区。着陆垫设置在下单元栅极图案之间。形成节点图案以同时接触上单元格栅图案和下单元栅格图案。

7. 发明授权

US07417286B2 Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same 有权
标题翻译：具有单晶薄膜晶体管的半导体集成电路器件及其制造方法
公开(公告)号：US07417286B2
公开(公告)日：2008-08-26
申请号：US11280045
申请日：2005-11-15
申请人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Jong-Hyuk Kim , Kun-Ho Kwak , Hoon Lim
发明人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Jong-Hyuk Kim , Kun-Ho Kwak , Hoon Lim
IPC分类号： H01L23/62
CPC分类号： H01L27/0688 , H01L21/8221
摘要： Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same are provided. The semiconductor integrated circuit devices include an interlayer insulating layer formed on a semiconductor substrate and a single crystalline semiconductor plug penetrating the interlayer insulating layer. A single crystalline semiconductor body pattern is provided on the interlayer insulating layer. The single crystalline semiconductor body pattern has an elevated region and contacts the single crystalline semiconductor plug. The method of forming the single crystalline semiconductor body pattern having the elevated region includes forming a sacrificial layer pattern covering the single crystalline semiconductor plug on the interlayer insulating layer. A capping layer is formed to cover the sacrificial layer pattern and the interlayer insulating layer, and the capping layer is patterned to form an opening which exposes a portion of the sacrificial layer pattern. Subsequently, the sacrificial layer pattern is selectively removed to form a cavity in the capping layer, and a planarized single crystalline semiconductor body pattern is formed to fill the cavity and the opening.
摘要翻译：提供具有单晶薄膜晶体管的半导体集成电路器件及其制造方法。半导体集成电路器件包括形成在半导体衬底上的层间绝缘层和贯穿层间绝缘层的单晶半导体插件。在层间绝缘层上设置单晶体半导体图案。单晶半导体主体图案具有升高的区域并与单晶半导体插头接触。形成具有升高区域的单晶半导体主体图案的方法包括在层间绝缘层上形成覆盖单晶半导体插塞的牺牲层图案。形成覆盖牺牲层图案和层间绝缘层的覆盖层，并且对覆盖层进行图案化以形成露出牺牲层图案的一部分的开口。随后，选择性地去除牺牲层图案以在封盖层中形成空腔，并且形成平坦化的单晶半导体主体图案以填充空腔和开口。

8. 发明授权

US07247528B2 Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques 失效
标题翻译：使用选择性外延生长和部分平面化技术制造半导体集成电路的方法
公开(公告)号：US07247528B2
公开(公告)日：2007-07-24
申请号：US11065750
申请日：2005-02-24
申请人： Kun-Ho Kwak , Jae-Hoon Jang , Soon-Moon Jung , Won-Seok Cho , Hoon Lim , Sung-Jin Kim , Byung-Jun Hwang , Jong-Hyuk Kim
发明人： Kun-Ho Kwak , Jae-Hoon Jang , Soon-Moon Jung , Won-Seok Cho , Hoon Lim , Sung-Jin Kim , Byung-Jun Hwang , Jong-Hyuk Kim
IPC分类号： H01L21/00
CPC分类号： H01L27/1108 , H01L27/11
摘要： Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.
摘要翻译：提供了使用SEG技术制造具有薄膜晶体管的半导体集成电路的方法。所述方法包括在单晶半导体衬底上形成层间绝缘层。单晶半导体插件延伸穿过层间绝缘层，并且单晶外延半导体图案与层间绝缘层上的单晶半导体插头接触。单晶外延半导体图案至少部分地平坦化以在层间绝缘层上形成半导体本体层，并且对半导体本体层进行图案化以形成半导体本体。结果，半导体本体包括单晶外延半导体图案的至少一部分。因此，半导体本体具有优异的单晶结构。还提供了使用这些方法制造的半导体集成电路。

9. 发明申请

US20050221544A1 Methods of fabricating semiconductor devices having thin film transistors 有权
标题翻译：制造具有薄膜晶体管的半导体器件的方法
公开(公告)号：US20050221544A1
公开(公告)日：2005-10-06
申请号：US11098648
申请日：2005-04-04
申请人： Kun-Ho Kwak , Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Hoon Lim , Jong-Hyuk Kim , Myang-Sik Han , Byung-Jun Hwang
发明人： Kun-Ho Kwak , Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Hoon Lim , Jong-Hyuk Kim , Myang-Sik Han , Byung-Jun Hwang
IPC分类号： H01L21/00 , H01L21/8244 , H01L21/84 , H01L27/06 , H01L27/11 , H01L27/12 , H01L29/15 , H01L29/786 , H01L31/0312
CPC分类号： H01L27/1108 , H01L27/0688 , H01L27/11 , H01L29/78603
摘要： Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.
摘要翻译：提供制造半导体器件的方法。层间绝缘层设置在单晶半导体衬底上。提供延伸穿过层间绝缘层的单晶半导体插头，并且在半导体衬底和单晶半导体插头上设置成型层图案。模制层图案限定其中的开口，其至少部分地暴露单晶半导体插塞的一部分。使用选择性外延生长技术在单晶半导体插塞的暴露部分上提供单晶半导体外延图案，其使用单晶半导体插塞的暴露部分作为籽晶层。在开口中设置单晶半导体区域。单晶半导体区域包括单晶半导体外延图案的至少一部分。

10. 发明授权

US07312110B2 Methods of fabricating semiconductor devices having thin film transistors 有权
标题翻译：制造具有薄膜晶体管的半导体器件的方法
公开(公告)号：US07312110B2
公开(公告)日：2007-12-25
申请号：US11098648
申请日：2005-04-04
申请人： Kun-Ho Kwak , Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Hoon Lim , Jong-Hyuk Kim , Myang-Sik Han , Byung-Jun Hwang
发明人： Kun-Ho Kwak , Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Hoon Lim , Jong-Hyuk Kim , Myang-Sik Han , Byung-Jun Hwang
IPC分类号： H01L21/00
CPC分类号： H01L27/1108 , H01L27/0688 , H01L27/11 , H01L29/78603
摘要： Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.
摘要翻译：提供制造半导体器件的方法。层间绝缘层设置在单晶半导体衬底上。提供延伸穿过层间绝缘层的单晶半导体插头，并且在半导体衬底和单晶半导体插头上设置成型层图案。模制层图案限定其中的开口，其至少部分地暴露单晶半导体插塞的一部分。使用选择性外延生长技术在单晶半导体插塞的暴露部分上提供单晶半导体外延图案，其使用单晶半导体插塞的暴露部分作为籽晶层。在开口中设置单晶半导体区域。单晶半导体区域包括单晶半导体外延图案的至少一部分。

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