专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07518420B1 Delay circuit limit detection circuit and method 有权
标题翻译：延迟电路限制检测电路及方法
公开(公告)号：US07518420B1
公开(公告)日：2009-04-14
申请号：US11699951
申请日：2007-01-30
申请人： Jonathon C. Stiff
发明人： Jonathon C. Stiff
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , H03K3/0315
摘要： A delay limit detect circuit can determine the delay of a current steering delay cell, like those utilized in a voltage controlled oscillator (VCO), by monitoring a current (ISENSE) that tracks a delay cell current (I2). When the monitored current (ISENSE) outside of a limit, a signal LIMIT can be activated. A monitored current (ISENSE) can be generated by a control replica circuit having the same circuit component types as a control circuit within a delay cell. Such limit detection can provide a way to prevent a ring VCO from entering a runaway state, particularly in cases where a maximum frequency can be reached before a maximum control voltage is reached.
摘要翻译：延迟限制检测电路可以通过监视跟踪延迟单元电流（I2）的电流（ISENSE）来确定电压转向延迟单元的延迟，如在压控振荡器（VCO）中使用的延迟单元的延迟。当监控电流（ISENSE）超出极限时，可以激活信号LIMIT。受监控电流（ISENSE）可以由具有与延迟单元内的控制电路相同的电路组件类型的控制复制电路产生。这种极限检测可以提供一种防止环形VCO进入失控状态的方法，特别是在达到最大控制电压之前可以达到最大频率的情况下。

2. 发明授权

US07394308B1 Circuit and method for implementing a low supply voltage current reference 有权
标题翻译：实现低电源电压参考电路和方法
公开(公告)号：US07394308B1
公开(公告)日：2008-07-01
申请号：US10796859
申请日：2004-03-08
申请人： Jonathon C. Stiff , Jay Kuhn
发明人： Jonathon C. Stiff , Jay Kuhn
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/262
摘要： A circuit for generating a reference current, comprising a positive feedback loop, a negative feedback loop, and a floating current mirror coupled to the positive feedback loop. The negative feedback loop may operate to divert current directly from the floating mirror, and may also operate to divert current from the floating mirror by using a voltage follower. The circuit may operate with a minimum supply voltage of approximately the sum of the threshold voltage of a transistor plus three drain saturation voltages, in one example.
摘要翻译：用于产生参考电流的电路，包括正反馈回路，负反馈回路和耦合到正反馈回路的浮动电流镜。负反馈环路可以操作以直接从浮动反射镜转移电流，并且还可以通过使用电压跟随器来操作以从浮动反射镜转移电流。在一个示例中，电路可以以大致为晶体管的阈值电压和三个漏极饱和电压的总和的最小电源电压进行操作。

3. 发明授权

US07295049B1 Method and circuit for rapid alignment of signals 有权
标题翻译：信号快速对准的方法和电路
公开(公告)号：US07295049B1
公开(公告)日：2007-11-13
申请号：US11088028
申请日：2005-03-22
申请人： Nathan Moyal , Jonathon C. Stiff
发明人： Nathan Moyal , Jonathon C. Stiff
IPC分类号： H03L7/06
CPC分类号： H03K5/135 , H03K5/156
摘要： Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.
摘要翻译：用于对准包括第一和第二信号的两个或多个信号的电路和方法。在一个实施例中，移位寄存器产生第二信号的两个或更多个偏移副本，并且多个相位检测器中的每一个接收第一信号和第二信号的移位副本之一，每个相位检测器提供一个输出，第一信号基本上与第二信号的偏移副本对准。还可以提供多路复用器用于接收第二信号的每个移位副本，多路复用器具有与相位检测器的输出信号耦合的多条选择线。一些实施例可以包括省电模式。

4. 发明授权

US06466078B1 Reduced static phase error CMOS PLL charge pump 有权
标题翻译：降低静态相位误差CMOS PLL电荷泵
公开(公告)号：US06466078B1
公开(公告)日：2002-10-15
申请号：US09849164
申请日：2001-05-04
申请人： Jonathon C. Stiff
发明人： Jonathon C. Stiff
IPC分类号： G05F110
CPC分类号： H03L7/0895
摘要： An apparatus comprising a pump up circuit, a pump down circuit and an output circuit. The pump up circuit may be configured to generate a pump up signal and receive a first source bias. The pump down circuit may be configured to generate a pump down signal and receive a second source bias. The output circuit may be configured to receive the pump up and pump down signals and generate an output signal. The pump up circuit may be configured to precharge the first source bias and the pump down circuit may be configured to precharge the second source bias signal.
摘要翻译：一种包括泵浦电路，抽空电路和输出电路的装置。泵浦电路可以被配置为产生泵浦信号并且接收第一源极偏置。抽吸电路可以被配置为产生抽空信号并接收第二源极偏置。输出电路可以被配置为接收泵浦并抽吸信号并产生输出信号。泵浦电路可以被配置为对第一源极偏压进行预充电，并且抽运电路可以被配置为对第二源极偏置信号进行预充电。

5. 发明授权

US07170319B1 Method and an apparatus to reduce duty cycle distortion 有权
标题翻译：降低占空比失真的方法和装置
公开(公告)号：US07170319B1
公开(公告)日：2007-01-30
申请号：US10962929
申请日：2004-10-11
申请人： Jonathon C. Stiff , King H. Kwan
发明人： Jonathon C. Stiff , King H. Kwan
IPC分类号： H03K19/094 , H03K19/0175 , H03K19/096 , H03L7/00
CPC分类号： H03K5/1565
摘要： A method and an apparatus to reduce duty cycle distortion are described. The apparatus may include a first current-mode logic (CML) circuit block comprising a positive input and a negative input and a second CML circuit block coupled in series to the first CML circuit block. The second CML circuit block may comprise a positive output, a negative output and a first transistor coupled between the positive input and the positive output. The second transistor may be coupled between the negative input and the negative output of the second CML circuit block.
摘要翻译：描述了减少占空比失真的方法和装置。该装置可以包括包括正输入和负输入的第一电流模式逻辑（CML）电路块，以及与第一CML电路块串联耦合的第二CML电路块。第二CML电路块可以包括正输出，负输出和耦合在正输入和正输出之间的第一晶体管。第二晶体管可以耦合在第二CML电路块的负输入和负输出之间。

6. 发明授权

US06911857B1 Current controlled delay circuit 有权
标题翻译：电流控制延时电路
公开(公告)号：US06911857B1
公开(公告)日：2005-06-28
申请号：US10305589
申请日：2002-11-26
申请人： Jonathon C. Stiff
发明人： Jonathon C. Stiff
IPC分类号： H03K3/356 , H03K5/00 , H03K5/13 , H03K17/041 , H03K17/28
CPC分类号： H03K5/133 , H03K3/356139 , H03K17/04106 , H03K2005/00026 , H03K2005/00208
摘要： A current controlled delay circuit is disclosed. Two currents of constant sum are generated to control the delay of the circuit. The circuit includes a differential pair to switch one of the two currents from one leg of the circuit to another leg of the circuit. The circuit includes a cross-coupled pair to switch the other of the two currents from one leg of the circuit to another leg of the circuit. The circuit may include a fixed or variable load.
摘要翻译：公开了一种电流控制延迟电路。产生两个恒定和的电流来控制电路的延迟。电路包括一个差分对，用于将两个电流中的一个从电路的一条支路切换到电路的另一条支路。电路包括交叉耦合对，以将两条电流中的另一条电流从电路的一条线路切换到电路的另一条支路。电路可以包括固定或可变负载。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式