专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08503164B2 Sintered capacitor electrode including a folded connection 有权
公开(公告)号：US08503164B2
公开(公告)日：2013-08-06
申请号：US12968555
申请日：2010-12-15
申请人： Gregory J. Sherwood , Jay E. Daley , Mary M. Byron , Eric Stemen , Peter Jay Kuhn
发明人： Gregory J. Sherwood , Jay E. Daley , Mary M. Byron , Eric Stemen , Peter Jay Kuhn
IPC分类号： H01G9/10
摘要： This document discusses capacitive elements including a first, second and third electrode arranged in a stack. The third electrode is positioned between the first and second electrode. An interconnect includes a unitary substrate shared with the first and second electrodes. The interconnect is adapted to deform to accommodate the stacked nature of the first and second electrodes. The unitary substrate includes a sintered material disposed thereon.

2. 发明申请

US20120270091A1 ELECTRICAL INSULATOR SHAPED TO CONFORM TO POWER SOURCE ELECTRODES 有权
标题翻译：电绝缘体形成为电源电极
公开(公告)号：US20120270091A1
公开(公告)日：2012-10-25
申请号：US13435240
申请日：2012-03-30
申请人： Peter Jay Kuhn , Brad Whitney , Matthew Wappel , Vanessa Mitchell , Kyle Richard Chlan
发明人： Peter Jay Kuhn , Brad Whitney , Matthew Wappel , Vanessa Mitchell , Kyle Richard Chlan
IPC分类号： H01M6/46 , H01M2/02 , H01G9/048 , H01M6/00
CPC分类号： H01G9/06 , H01G9/08 , H01M2/026 , H01M2/0277 , H01M2/22 , H01M2/266 , H01M6/46 , H01M10/0468 , H01M10/0477 , H01M10/049 , H01M2220/30 , Y10T29/49108 , Y10T29/49114
摘要： One example includes a plurality of substantially planar electrodes disposed in a stack, in alignment, the stack being at least partially disk-shaped with a first major face opposing a second major face, with an edge extending between the first major face and the second major face, a pocket, with a covered portion of the stack disposed in the pocket, the pocket shaped to conform to the stack with a first portion of the pocket covering a first segment of the first major face, a second portion covering a second segment of the second major face opposite the first segment, and an edge portion covering the edge of the stack, wherein a remaining portion of the stack extends out of the pocket and a film disposed over the remaining portion of the stack, substantially covering the remaining portion.
摘要翻译：一个示例包括布置在堆叠中的多个基本上平面的电极，其对齐，所述堆叠至少部分地具有盘形，其具有与第二主面相对的第一主面，边缘在第一主面和第二主面之间延伸面部，口袋，其中堆叠物的被覆部分设置在口袋中，口袋成形为符合堆叠，袋的第一部分覆盖第一主面的第一部分，第二部分覆盖第二部分第二主面与第一段相对，以及覆盖堆叠边缘的边缘部分，其中堆叠的剩余部分延伸出口袋，并且薄膜设置在堆叠的剩余部分上，基本覆盖剩余部分。

3. 发明申请

US20110152958A1 SINTERED ELECTRODES TO STORE ENERGY IN AN IMPLANTABLE MEDICAL DEVICE 有权
标题翻译：烧结电极在可植入医疗器械中储存能量
公开(公告)号：US20110152958A1
公开(公告)日：2011-06-23
申请号：US12968523
申请日：2010-12-15
申请人： Gregory J. Sherwood , Michael J. Root , Peter Jay Kuhn , Mary M. Byron , Eric Stemen
发明人： Gregory J. Sherwood , Michael J. Root , Peter Jay Kuhn , Mary M. Byron , Eric Stemen
IPC分类号： A61N1/39 , H01G9/10
CPC分类号： H01G9/08 , A61N1/375 , A61N1/3782 , H01G9/008 , H01G9/052 , H01G9/06 , Y10T29/417
摘要： An example includes a capacitor case sealed to retain electrolyte, at least one anode disposed in the capacitor case, the at least one anode comprising a sintered portion disposed on a substrate, an anode conductor coupled to the substrate in electrical communication with the sintered portion, the anode conductor sealingly extending through the capacitor case to an anode terminal disposed on the exterior of the capacitor case with the anode terminal in electrical communication with the sintered portion, a cathode disposed in the capacitor case, a separator disposed between the cathode and the anode and a cathode terminal disposed on an exterior of the capacitor case and in electrical communication with the cathode, with the anode terminal and the cathode terminal electrically isolated from one another.
摘要翻译：一个实例包括密封以保持电解质的电容器壳体，设置在电容器壳体中的至少一个阳极，至少一个阳极包括设置在基板上的烧结部分，与该烧结部分电连通的与该基板相连的阳极导体，所述阳极导体密封地延伸穿过所述电容器壳体到设置在所述电容器外壳的外部的阳极端子，所述阳极端子与所述烧结部分电连通，设置在所述电容器壳体中的阴极，设置在所述阴极和所述阳极之间的隔板以及设置在电容器壳体的外部并与阴极电连通的阴极端子，阳极端子和阴极端子彼此电隔离。

4. 发明申请

US20070139244A1 CAPACITIVE LEVEL SHIFTING FOR ANALOG SIGNAL PROCESSING 有权
标题翻译：用于模拟信号处理的电容水平移位
公开(公告)号：US20070139244A1
公开(公告)日：2007-06-21
申请号：US11313549
申请日：2005-12-20
申请人： Jay Kuhn
发明人： Jay Kuhn
IPC分类号： H03M1/12
CPC分类号： H03M1/1061 , H03M1/361
摘要： An analog processing block is arranged to receive an input signal through an AC coupling circuit. A digitally programmable voltage reference (DPVR) circuit is arranged to provide selection of a voltage reference that is DC coupled through a high impedance circuit to the AC coupling circuit. The input to the analog processing block includes the AC coupled input signal and the DC level from the selected voltage reference such that the DC level is effectively shifted for the analog processing block. The analog processing block may include any number of analog functions including: buffering, level shifting, scaling, integrating, and analog-to-digital conversion for digital signal processing, to name a few. A digital control logic circuit and a trim map can be arranged to control adjustments to the DPVR such that the effects of any non-ideal conditions on the analog processing block are minimized. The trim map may include non-volatile memory devices.
摘要翻译：模拟处理块被布置成通过AC耦合电路接收输入信号。数字可编程电压基准（DPVR）电路被布置成提供通过高阻抗电路直流耦合到AC耦合电路的电压参考的选择。对模拟处理块的输入包括AC耦合的输入信号和来自所选电压基准的DC电平，使得对于模拟处理块有效地移位DC电平。模拟处理块可以包括任何数量的模拟功能，包括：数字信号处理的缓冲，电平转换，缩放，积分和模数转换，仅举几个例子。可以布置数字控制逻辑电路和修剪图以控制对DPVR的调整，使得任何非理想条件对模拟处理块的影响最小化。修剪图可以包括非易失性存储器件。

5. 发明授权

US09129749B2 Sintered electrodes to store energy in an implantable medical device 有权
标题翻译：烧结电极，用于在可植入医疗器械中储存能量
公开(公告)号：US09129749B2
公开(公告)日：2015-09-08
申请号：US12968523
申请日：2010-12-15
申请人： Gregory J. Sherwood , Michael J. Root , Peter Jay Kuhn , Mary M. Byron , Eric Stemen
发明人： Gregory J. Sherwood , Michael J. Root , Peter Jay Kuhn , Mary M. Byron , Eric Stemen
IPC分类号： A61N1/39 , H01G9/08 , H01G9/008 , H01G9/052 , H01G9/06 , A61N1/375 , A61N1/378
CPC分类号： H01G9/08 , A61N1/375 , A61N1/3782 , H01G9/008 , H01G9/052 , H01G9/06 , Y10T29/417
摘要： An example includes a capacitor case sealed to retain electrolyte, at least one anode disposed in the capacitor case, the at least one anode comprising a sintered portion disposed on a substrate, an anode conductor coupled to the substrate in electrical communication with the sintered portion, the anode conductor sealingly extending through the capacitor case to an anode terminal disposed on the exterior of the capacitor case with the anode terminal in electrical communication with the sintered portion, a cathode disposed in the capacitor case, a separator disposed between the cathode and the anode and a cathode terminal disposed on an exterior of the capacitor case and in electrical communication with the cathode, with the anode terminal and the cathode terminal electrically isolated from one another.
摘要翻译：一个实例包括密封以保持电解质的电容器壳体，设置在电容器壳体中的至少一个阳极，至少一个阳极包括设置在基板上的烧结部分，与该烧结部分电连通的与该基板相连的阳极导体，所述阳极导体密封地延伸穿过所述电容器壳体到设置在所述电容器外壳的外部的阳极端子，所述阳极端子与所述烧结部分电连通，设置在所述电容器壳体中的阴极，设置在所述阴极和所述阳极之间的隔板以及设置在电容器壳体的外部并与阴极电连通的阴极端子，阳极端子和阴极端子彼此电隔离。

6. 发明授权

US08952792B1 Self tuning RFID tags 有权
标题翻译：自调整RFID标签
公开(公告)号：US08952792B1
公开(公告)日：2015-02-10
申请号：US13345654
申请日：2012-01-06
申请人： Shailendra Srinivas , Jay Kuhn , Ronald A. Oliver , John D. Hyde , Christopher J. Diorio
发明人： Shailendra Srinivas , Jay Kuhn , Ronald A. Oliver , John D. Hyde , Christopher J. Diorio
IPC分类号： H04Q5/22 , G08B13/14 , H01Q1/24 , H01Q11/12 , H02M7/519
CPC分类号： G06K19/0715 , G06K19/0709 , H01Q1/2208 , H01Q1/248 , H01Q5/335 , H03H7/38 , H04Q2213/13095
摘要： A tuning circuit in an RFID tag may be used to match antenna and integrated circuit (IC) impedances to maximize the efficiency of IC power extraction from an incident RF wave. The tuning circuit, which requires less power to operate than the IC, adjusts a variable impedance to improve the impedance matching between the IC and the tag antenna and thereby increase the IC power extraction efficiency. The IC may begin operating according to a protocol when it extracts sufficient power from the RF wave or when an optimal impedance matching and power transfer is achieved.
摘要翻译：可以使用RFID标签中的调谐电路来匹配天线和集成电路（IC）阻抗，以使来自入射RF波的IC功率提取的效率最大化。与IC相比，调谐电路需要更少的功率来调节可变阻抗，以改善IC和标签天线之间的阻抗匹配，从而提高IC功率提取效率。当IC从RF波提取足够的功率或当达到最佳的阻抗匹配和功率传输时，IC可以根据协议开始操作。

7. 发明申请

US20110149475A1 SINTERED CAPACITOR ELECTRODE INCLUDING A FOLDED CONNECTION 有权
标题翻译：烧结电极包括折叠连接
公开(公告)号：US20110149475A1
公开(公告)日：2011-06-23
申请号：US12968555
申请日：2010-12-15
申请人： Gregory J. Sherwood , Jay E. Daley , Mary M. Byron , Eric Stemen , Peter Jay Kuhn
发明人： Gregory J. Sherwood , Jay E. Daley , Mary M. Byron , Eric Stemen , Peter Jay Kuhn
IPC分类号： H01G9/10 , H05K5/00
CPC分类号： H01G9/045 , A61N1/375 , A61N1/3782 , H01G9/0029 , H01G9/008 , H01G9/048 , H01G9/052 , H01G9/06 , H01G9/08 , H01G9/14 , H01G9/15 , Y10T29/417
摘要： This document discusses capacitive elements including a first, second and third electrode arranged in a stack. The third electrode is positioned between the first and second electrode. An interconnect includes a unitary substrate shared with the first and second electrodes. The interconnect is adapted to deform to accommodate the stacked nature of the first and second electrodes. The unitary substrate includes a sintered material disposed thereon.
摘要翻译：本文讨论了包括以堆叠布置的第一，第二和第三电极的电容元件。第三电极位于第一和第二电极之间。互连包括与第一和第二电极共享的整体衬底。互连件适于变形以适应第一和第二电极的层叠性质。整体式基板包括设置在其上的烧结材料。

8. 发明授权

US07394308B1 Circuit and method for implementing a low supply voltage current reference 有权
标题翻译：实现低电源电压参考电路和方法
公开(公告)号：US07394308B1
公开(公告)日：2008-07-01
申请号：US10796859
申请日：2004-03-08
申请人： Jonathon C. Stiff , Jay Kuhn
发明人： Jonathon C. Stiff , Jay Kuhn
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/262
摘要： A circuit for generating a reference current, comprising a positive feedback loop, a negative feedback loop, and a floating current mirror coupled to the positive feedback loop. The negative feedback loop may operate to divert current directly from the floating mirror, and may also operate to divert current from the floating mirror by using a voltage follower. The circuit may operate with a minimum supply voltage of approximately the sum of the threshold voltage of a transistor plus three drain saturation voltages, in one example.
摘要翻译：用于产生参考电流的电路，包括正反馈回路，负反馈回路和耦合到正反馈回路的浮动电流镜。负反馈环路可以操作以直接从浮动反射镜转移电流，并且还可以通过使用电压跟随器来操作以从浮动反射镜转移电流。在一个示例中，电路可以以大致为晶体管的阈值电压和三个漏极饱和电压的总和的最小电源电压进行操作。

9. 发明授权

US08974949B2 Electrical insulator shaped to conform to power source electrodes 有权
标题翻译：电绝缘体成形为符合电源电极
公开(公告)号：US08974949B2
公开(公告)日：2015-03-10
申请号：US13435240
申请日：2012-03-30
申请人： Peter Jay Kuhn , Brad Whitney , Matthew Wappel , Vanessa Mitchell , Kyle Richard Chlan
发明人： Peter Jay Kuhn , Brad Whitney , Matthew Wappel , Vanessa Mitchell , Kyle Richard Chlan
IPC分类号： H01M6/12 , H01G9/06 , H01G9/08 , H01M6/46 , H01M2/02 , H01M2/22 , H01M2/26 , H01M10/04
CPC分类号： H01G9/06 , H01G9/08 , H01M2/026 , H01M2/0277 , H01M2/22 , H01M2/266 , H01M6/46 , H01M10/0468 , H01M10/0477 , H01M10/049 , H01M2220/30 , Y10T29/49108 , Y10T29/49114
摘要： One example includes a plurality of substantially planar electrodes disposed in a stack, in alignment, the stack being at least partially disk-shaped with a first major face opposing a second major face, with an edge extending between the first major face and the second major face, a pocket, with a covered portion of the stack disposed in the pocket, the pocket shaped to conform to the stack with a first portion of the pocket covering a first segment of the first major face, a second portion covering a second segment of the second major face opposite the first segment, and an edge portion covering the edge of the stack, wherein a remaining portion of the stack extends out of the pocket and a film disposed over the remaining portion of the stack, substantially covering the remaining portion.
摘要翻译：一个示例包括布置在堆叠中的多个基本上平面的电极，其对齐，所述堆叠至少部分地具有盘形，其具有与第二主面相对的第一主面，边缘在第一主面和第二主面之间延伸面部，口袋，其中堆叠物的被覆部分设置在口袋中，口袋成形为符合堆叠，袋的第一部分覆盖第一主面的第一部分，第二部分覆盖第二部分第二主面与第一段相对，以及覆盖堆叠边缘的边缘部分，其中堆叠的剩余部分延伸出口袋，并且薄膜设置在堆叠的剩余部分上，基本覆盖剩余部分。

10. 发明申请

US20070172966A1 Automatic on-die defect isolation 有权
标题翻译：自动模内缺陷隔离
公开(公告)号：US20070172966A1
公开(公告)日：2007-07-26
申请号：US11336161
申请日：2006-01-20
申请人： John Hyde , Jay Kuhn , Ronald Koepp , Ronald Paulsen
发明人： John Hyde , Jay Kuhn , Ronald Koepp , Ronald Paulsen
IPC分类号： H01L21/66
CPC分类号： G01R31/2884 , G01R31/2831 , H01L22/32
摘要： Microcircuits may include polysilicon features that are vulnerable to defects due to undesirable phenomena during manufacturing processes such as, inter alia, over-etching. The same phenomena that may cause defects can be exploited to automatically isolate the affected circuit and thus limit the harm caused by defects or incipient defects.
摘要翻译：微电路可以包括由于在制造过程中的不期望的现象（例如过度蚀刻）而容易受到缺陷的多晶硅特征。可以利用可能引起缺陷的相同现象来自动隔离受影响的电路，从而限制由缺陷或初始缺陷引起的危害。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式