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1. 发明授权

US07147499B1 Zero insertion force printed circuit assembly connector system and method 有权
标题翻译：零插入力印刷电路组件连接器系统和方法
公开(公告)号：US07147499B1
公开(公告)日：2006-12-12
申请号：US11253446
申请日：2005-10-19
申请人： Romi Mayder , John W. Andberg , Don Chiu , Noriyuki Sugihara
发明人： Romi Mayder , John W. Andberg , Don Chiu , Noriyuki Sugihara
IPC分类号： H01R13/62
CPC分类号： G01R31/2889
摘要： In one embodiment, a mating circuit assembly is coupled and decoupled to a system by 1) mechanically and electrically coupling at least a first interposer, mounted on at least one of first and second substrates, to the mating circuit assembly. The mechanical and electrical coupling is accomplished using at least first and second spring mechanisms, with the first and second spring mechanisms being mounted between the connector housing and respective ones of the first and second substrates. At least one of the first and second substrates transmits signals between the first interposer and the system. The first interposer is electrically and mechanically decoupled from the mating circuit assembly by creating a vacuum between the connector housing and at least one of the first and second substrates. Other embodiments are also disclosed.
摘要翻译：在一个实施例中，匹配电路组件通过1）将安装在第一和第二衬底中的至少一个上的至少第一插入件机械地和电耦合到配合电路组件而耦合到系统。使用至少第一和第二弹簧机构实现机械和电耦合，其中第一和第二弹簧机构安装在连接器壳体与第一和第二基板中的相应的基板之间。第一和第二基板中的至少一个在第一插入器和系统之间传输信号。第一插入器通过在连接器壳体与第一和第二基板中的至少一个之间产生真空而与配合电路组件电气和机械地分离。还公开了其他实施例。

2. 发明申请

US20140070828A1 METHOD AND APPARATUS FOR MASSIVELY PARALLEL MULTI-WAFER TEST 有权
标题翻译：用于大规模并行多波长测试的方法和装置
公开(公告)号：US20140070828A1
公开(公告)日：2014-03-13
申请号：US13609154
申请日：2012-09-10
申请人： John W. Andberg , Ira H. Leventhal , Matthew W. Losey , Yohannes Desta , Lakshmikanth Namburi , Vincent E. Lopopolo , Sanjeev Grover , Erik Volkerink
发明人： John W. Andberg , Ira H. Leventhal , Matthew W. Losey , Yohannes Desta , Lakshmikanth Namburi , Vincent E. Lopopolo , Sanjeev Grover , Erik Volkerink
IPC分类号： G01R1/073 , G01R35/00 , G01R1/04
CPC分类号： G01R1/073 , G01R1/0408 , G01R31/2891 , G01R31/2893 , G01R35/005
摘要： Disclosed herein is a cost effective, efficient, massively parallel multi-wafer test cell. Additionally, this test cell can be used for both single-touchdown and multiple-touchdown applications. The invention uses a novel “split-cartridge” design, combined with a method for aligning wafers when they are separated from the probe card assembly, to create a cost effective, efficient multi-wafer test cell. A “probe-card stops” design may be used within the cartridge to simplify the overall cartridge design and operation.
摘要翻译：本文公开了一种成本有效，高效，大规模并行的多晶圆测试电池。此外，该测试单元可用于单触地板和多触地应用。本发明使用新颖的“分离式墨盒”设计，结合将晶片与探针卡组件分离时对准的方法，以创建成本有效的，高效的多晶圆测试单元。可以在墨盒内使用“探针卡停止”设计，以简化总体墨盒的设计和操作。

3. 发明申请

US20100134134A1 TEST ELECTRONICS TO DEVICE UNDER TEST INTERFACES, AND METHODS AND APPARATUS USING SAME 有权
标题翻译：测试电子仪器在测试接口下的设备，以及使用它的方法和设备
公开(公告)号：US20100134134A1
公开(公告)日：2010-06-03
申请号：US12626506
申请日：2009-11-25
申请人： Sanjeev Grover , Donald W. Chiu , John W. Andberg
发明人： Sanjeev Grover , Donald W. Chiu , John W. Andberg
IPC分类号： G01R31/02
CPC分类号： G01R31/2601 , G01R31/2889
摘要： In one embodiment, a test system has a set of test electronics for testing a device under test (DUT). The test system also has at least one test electronics to DUT interface having a zero insertion force (ZIF) connector. Each ZIF connector has a ZIF connector to DUT clamping mechanism configured to i) apply a first orthogonal force to a probe card that interfaces with a DUT, by pressing the ZIF connector against the probe card, and simultaneously ii) exert at least one second orthogonal force on the probe card, the at least one second orthogonal force being opposite in direction to the first orthogonal force.
摘要翻译：在一个实施例中，测试系统具有用于测试被测设备（DUT）的一组测试电子装置。测试系统还具有至少一个具有零插入力（ZIF）连接器的DUT接口的测试电子器件。每个ZIF连接器具有ZIF连接器到DUT夹持机构，该ZIF连接器被配置为：i）通过将ZIF连接器压靠在探针卡上，向与DUT接口的探针卡施加第一正交力，并且同时施加至少一个第二正交所述至少一个第二正交力在与所述第一正交力相反的方向上相反。

4. 发明授权

US09335347B2 Method and apparatus for massively parallel multi-wafer test 有权
标题翻译：用于大规模并行多晶片测试的方法和装置
公开(公告)号：US09335347B2
公开(公告)日：2016-05-10
申请号：US13609154
申请日：2012-09-10
申请人： John W. Andberg , Ira H. Leventhal , Matthew W. Losey , Yohannes Desta , Lakshmikanth Namburi , Vincent E. Lopopolo , Sanjeev Grover , Erik Volkerink
发明人： John W. Andberg , Ira H. Leventhal , Matthew W. Losey , Yohannes Desta , Lakshmikanth Namburi , Vincent E. Lopopolo , Sanjeev Grover , Erik Volkerink
IPC分类号： G01R31/28 , G01R1/04 , G01R1/073 , G01R35/00
CPC分类号： G01R1/073 , G01R1/0408 , G01R31/2891 , G01R31/2893 , G01R35/005
摘要： Disclosed herein is a cost effective, efficient, massively parallel multi-wafer test cell. Additionally, this test cell can be used for both single-touchdown and multiple-touchdown applications. The invention uses a novel “split-cartridge” design, combined with a method for aligning wafers when they are separated from the probe card assembly, to create a cost effective, efficient multi-wafer test cell. A “probe-card stops” design may be used within the cartridge to simplify the overall cartridge design and operation.
摘要翻译：本文公开了一种成本有效，高效，大规模并行的多晶圆测试电池。此外，该测试单元可用于单触地板和多触地应用。本发明使用新颖的“分离式墨盒”设计，结合将晶片与探针卡组件分离时对准的方法，以创建成本有效的，高效的多晶圆测试单元。可以在墨盒内使用“探针卡停止”设计，以简化总体墨盒的设计和操作。

5. 发明授权

US6140616A Wafer level burn-in and test thermal chuck and method 有权
标题翻译：晶圆级老化和测试热卡盘及方法
公开(公告)号：US6140616A
公开(公告)日：2000-10-31
申请号：US161323
申请日：1998-09-25
申请人： John W. Andberg
发明人： John W. Andberg
IPC分类号： G01R31/26 , G01R31/30 , H01L21/00 , H01L21/66 , H01L21/683 , H05B3/68 , C23C16/00
CPC分类号： H01L21/67248 , H01L21/67103
摘要： A thermal chuck or heat sink (10) has a lower surface (12) covered with fins (14) parallel to air flow (16), to increase the surface area and promote heat transfer. A pair of slots (32) near pedestal (20) (along the fins) effectively lowers the conductivity of the metal in the direction across the fins. Heat flowing through this region of lowered conductivity experiences a greater temperature drop. This raises the temperature at the adjacent parts of the top surface, and (for properly sized slots) results in circular isotherms. The circular isotherms are turned into a nearly isothermal surface by a precisely dimensioned groove (36) parallel to the top surface (22), extending around the circumference of the pedestal (20). Heat flowing into the outer regions of the circular surface (22) is forced to travel radially inward, thus raising the edge temperature (which would naturally be lower than the center). For properly sized slots (32) and groove (36), it is possible to achieve a nearly constant temperature top surface (22).
摘要翻译：热卡盘或散热器（10）具有覆盖有与空气流（16）平行的翅片（14）的下表面（12），以增加表面积并促进热传递。靠近基座（20）（沿着翅片）的一对槽（32）有效地降低金属沿着翅片的方向的导电性。流过该区域的热量降低的热量经历较大的温度下降。这提高了顶部表面相邻部分的温度，并且（对于适当尺寸的狭槽）导致圆形等温线。圆形等温线通过平行于顶表面（22）的精确尺寸的凹槽（36）变成几乎等温的表面，围绕基座（20）的圆周延伸。流入圆形表面（22）的外部区域的热量被迫径向向内行进，从而提高边缘温度（这自然会低于中心点）。对于适当尺寸的槽（32）和槽（36），可以实现几乎恒定的温度顶表面（22）。

6. 发明申请

US20130135002A1 TEST ELECTRONICS TO DEVICE UNDER TEST INTERFACES, AND METHODS AND APPARATUS USING SAME 审中-公开
标题翻译：测试电子仪器在测试接口下的设备，以及使用它的方法和设备
公开(公告)号：US20130135002A1
公开(公告)日：2013-05-30
申请号：US13742183
申请日：2013-01-15
申请人： Sanjeev Grover , Donald W. Chiu , John W. Andberg
发明人： Sanjeev Grover , Donald W. Chiu , John W. Andberg
IPC分类号： G01R31/26
CPC分类号： G01R31/2601 , G01R31/2889
摘要： In one embodiment, an interface includes a plurality of test electronics to DUT interfaces. Each test electronics to DUT interface has at least one test electronics interface, at least one DUT interface, and an electrical coupling between the at least one test electronics interface and the at least one DUT interface. First and second subsets of the DUT interfaces are respectively positioned along the perimeters of first and second concentric shapes.
摘要翻译：在一个实施例中，接口包括多个测试电子器件到DUT接口。每个测试电子设备到DUT接口具有至少一个测试电子接口，至少一个DUT接口以及所述至少一个测试电子接口和所述至少一个DUT接口之间的电耦合。 DUT接口的第一和第二子集分别沿着第一和第二同心形状的周边定位。

7. 发明授权

US08354853B2 Test electronics to device under test interfaces, and methods and apparatus using same 有权
标题翻译：测试电子设备到被测设备的接口，以及使用它们的方法和设备
公开(公告)号：US08354853B2
公开(公告)日：2013-01-15
申请号：US12626506
申请日：2009-11-25
申请人： Sanjeev Grover , Donald W. Chiu , John W. Andberg
发明人： Sanjeev Grover , Donald W. Chiu , John W. Andberg
IPC分类号： G01R31/00
CPC分类号： G01R31/2601 , G01R31/2889
摘要： In one embodiment, a test system has a set of test electronics for testing a device under test (DUT). The test system also has at least one test electronics to DUT interface having a zero insertion force (ZIF) connector. Each ZIF connector has a ZIF connector to DUT clamping mechanism configured to i) apply a first orthogonal force to a probe card that interfaces with a DUT, by pressing the ZIF connector against the probe card, and simultaneously ii) exert at least one second orthogonal force on the probe card, the at least one second orthogonal force being opposite in direction to the first orthogonal force.
摘要翻译：在一个实施例中，测试系统具有用于测试被测设备（DUT）的一组测试电子装置。测试系统还具有至少一个具有零插入力（ZIF）连接器的DUT接口的测试电子器件。每个ZIF连接器具有ZIF连接器到DUT夹持机构，该ZIF连接器被配置为：i）通过将ZIF连接器压靠在探针卡上，向与DUT接口的探针卡施加第一正交力，并且同时施加至少一个第二正交所述至少一个第二正交力在与所述第一正交力相反的方向上相反。

8. 发明授权

US07459921B2 Method and apparatus for a paddle board probe card 有权
标题翻译：桨板探针卡的方法和装置
公开(公告)号：US07459921B2
公开(公告)日：2008-12-02
申请号：US11444645
申请日：2006-05-31
申请人： Romi Mayder , John W. Andberg
发明人： Romi Mayder , John W. Andberg
IPC分类号： G01R31/02
CPC分类号： G01R31/2889
摘要： A paddle board probe card for connecting a device under test with an ATE tester by means of ZIF connectors is presented. The paddle board probe card may include more than one printed circuit board mounted on a probe card in such a manner that the more than one printed circuit boards mate with ZIF connectors on an ATE testhead interface.
摘要翻译：提出了一种用于通过ZIF连接器将待测器件与ATE测试仪连接的桨板探针卡。桨板探针卡可以包括安装在探针卡上的多于一个印刷电路板，使得多于一个印刷电路板与ATE测试头接口上的ZIF连接器配合。

9. 发明申请

US20070296424A1 Method and apparatus for a paddle board probe card 有权
标题翻译：桨板探针卡的方法和装置
公开(公告)号：US20070296424A1
公开(公告)日：2007-12-27
申请号：US11444645
申请日：2006-05-31
申请人： Romi Mayder , John W. Andberg
发明人： Romi Mayder , John W. Andberg
IPC分类号： G01R31/02
CPC分类号： G01R31/2889
摘要： A paddle board probe card for connecting a device under test with an ATE tester by means of ZIF connectors is presented. The paddle board probe card may include more than one printed circuit board mounted on a probe card in such a manner that the more than one printed circuit boards mate with ZIF connectors on an ATE testhead interface.
摘要翻译：提出了一种用于通过ZIF连接器将待测器件与ATE测试仪连接的桨板探针卡。桨板探针卡可以包括安装在探针卡上的多于一个印刷电路板，使得多于一个印刷电路板与ATE测试头接口上的ZIF连接器配合。

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