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1. 发明授权

US4711118A Detection of water entrapped in electronic components 失效
标题翻译：水包埋在电子元件中的检测
公开(公告)号：US4711118A
公开(公告)日：1987-12-08
申请号：US318330
申请日：1981-11-05
申请人： Peter R. Bossard , John A. Mucha
发明人： Peter R. Bossard , John A. Mucha
IPC分类号： G01N21/35 , G01N21/39 , G01N21/94 , G01N21/00 , G01M3/00
CPC分类号： G01N21/94 , G01N21/3554 , G01N21/39
摘要： The accuracy of measurements made to determine the extent of water vapor trapped upon encapsulation of an electronic device is significantly enhanced by carefully controlling the measurement technique employed. In particular, the encapsulant is generally punctured and the water vapor thus released is monitored. It has been found that to obtain an accurate measurement of the magnitude of the water vapor released, this measurement must be made within 0.1 second of the time of encapsulant punctured and released into a glass system. By using an absorption technique with suitable electronics, this time requirement is fulfilled and significantly more accurate quantitative measurements of entrapped water vapor are obtained.
摘要翻译：通过仔细控制所采用的测量技术，可以显着提高用于确定电子设备封装时捕获的水蒸气的程度的测量精度。特别地，密封剂通常被刺穿并且监测如此释放的水蒸气。已经发现，为了获得对所释放的水蒸汽的大小的精确测量，该测量必须在密封剂刺穿和释放到玻璃体系中的0.1秒之内进行。通过使用具有合适电子元件的吸收技术，满足此时间要求，并获得明显更精确的捕获水蒸汽的定量测量。

2. 发明授权

US4960656A Devices and process for producing devices containing silicon nitride films 失效
标题翻译：用于生产含有氮化硅膜的器件的器件和工艺
公开(公告)号：US4960656A
公开(公告)日：1990-10-02
申请号：US449467
申请日：1989-12-12
申请人： Chorng-Ping Chang , Daniel L. Flamm , Dale E. Ibbotson , John A. Mucha
发明人： Chorng-Ping Chang , Daniel L. Flamm , Dale E. Ibbotson , John A. Mucha
IPC分类号： H01L21/318
CPC分类号： H01L21/3185
摘要： Silicon nitride regions suitable for applications such as capping layers in integrated circuit fabrication are produced by an advantageous plasma deposition process. This process utilizes a combination of gases, including a silicon-containing gas, a nitrogen-containing gas, a fluorine-containing gas, and a hydrogen-containing gas. Silicon nitride having a low density of defect states and thus having excellent dielectric properties is produced.
摘要翻译：通过有利的等离子体沉积工艺制造适合于集成电路制造中的覆盖层等应用的氮化硅区域。该方法利用包括含硅气体，含氮气体，含氟气体和含氢气体的气体的组合。产生具有低密度缺陷状态并因此具有优异介电特性的氮化硅。

3. 发明授权

US4498953A Etching techniques 失效
标题翻译：蚀刻技术
公开(公告)号：US4498953A
公开(公告)日：1985-02-12
申请号：US517754
申请日：1983-07-27
申请人： Joel M. Cook , Vincent M. Donnelly , Daniel L. Flamm , Dale E. Ibbotson , John A. Mucha
发明人： Joel M. Cook , Vincent M. Donnelly , Daniel L. Flamm , Dale E. Ibbotson , John A. Mucha
IPC分类号： H01L21/302 , C04B41/53 , C09K13/08 , C23C16/44 , C23F1/12 , H01L21/3065 , H01L21/311 , H01L21/3213 , B44C1/22 , C03C15/00 , C03C25/06 , C23F1/02
CPC分类号： C04B41/5346 , C09K13/08 , C23C16/4405 , C23F1/12 , H01L21/3065 , H01L21/31116 , H01L21/32136 , H01L21/32137 , Y10S148/105
摘要： A highly selective--greater than 100 to 1--etch for silicon, tantalum, tantalum silicide and tantalum nitride is achieved by using polyatomic halogen fluorides. The selectivity is achievable without employing plasmas or wet etching.
摘要翻译：通过使用多原子卤素氟化物可实现对硅，钽，硅化钽和氮化钽的高选择性 - 大于100至1蚀刻。无需使用等离子体或湿蚀刻即可实现选择性。

4. 发明授权

US06682999B1 Semiconductor device having multilevel interconnections and method of manufacture thereof 失效
标题翻译：具有多层互连的半导体器件及其制造方法
公开(公告)号：US06682999B1
公开(公告)日：2004-01-27
申请号：US09426124
申请日：1999-10-22
申请人： John A. Mucha
发明人： John A. Mucha
IPC分类号： H01L214763
CPC分类号： H01L21/76852 , H01L21/7682 , H01L21/76838 , H01L21/76856 , H01L21/76858 , H01L21/76873 , H01L21/76885 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides, in one aspect, a method for fabricating an interconnect system within a semiconductor device. In this particular embodiment, the method comprises forming a conductive layer over a substrate of the semiconductor device, such as a dielectric material, forming a photoresist layer over the conductive layer and patterning the photoresist, forming a selected portion and an unselected portion of the conductive layer, altering the selected portion such that the selected portion has an etch rate different from an etch rate of the unselected portion, and forming an interconnect on the selected or unselected portion. As used herein, the selected portion is defined as that portion of the conductive layer, such as a blanket seed layer, that is subject to the alteration process as discussed herein. The selected portion may be, depending on the embodiment, within a footprint of the interconnect or outside the footprint of the interconnect.
摘要翻译：本发明在一个方面提供一种在半导体器件内制造互连系统的方法。在该特定实施例中，该方法包括在半导体器件的衬底（例如电介质材料）的上方形成导电层，在导电层上形成光致抗蚀剂层并构图光致抗蚀剂，形成导电的选定部分和未选择的部分改变所选择的部分，使得所选择的部分具有与未选择部分的蚀刻速率不同的蚀刻速率，以及在所选择的或未选择的部分上形成互连。如本文所使用的，所选择的部分被定义为如本文所讨论的改变过程的导电层（例如覆盖种子层）的那部分。取决于实施例，所选择的部分可以在互连的占用面积内或互连的占地面积之外。

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