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1. 发明授权

US08606193B2 RF transceiver IC having internal loopback conductor for IP2 self test 有权
标题翻译： RF收发器IC具有用于IP2自检的内部回送导体
公开(公告)号：US08606193B2
公开(公告)日：2013-12-10
申请号：US12270755
申请日：2008-11-13
申请人： Jin-Su Ko , Michael Kohlmann , Bahman Ahrari
发明人： Jin-Su Ko , Michael Kohlmann , Bahman Ahrari
IPC分类号： H04B1/38
CPC分类号： H04B1/40 , H03D7/168
摘要： An RF transceiver integrated circuit has a novel segmented, low parasitic capacitance, internal loopback conductor usable for conducting IP2 self testing and/or calibration. In a first novel aspect, the transmit mixer of the transceiver is a current mode output mixer. The receive mixer is a passive mixer that has a low input impedance. In the loopback mode, the transmit mixer drives a two tone current signal to the passive mixer via the loopback conductor. In a second novel aspect, only one quadrature branch of the transmit mixer is used to generate both tones required for carrying out an IP2 test. In a third novel aspect, a first calibration test is performed using one quadrature branch of the transmit mixer at the same time that a second calibration test is performed using the other quadrature branch, thereby reducing loopback test time and power consumption.
摘要翻译： RF收发器集成电路具有新颖的分段，低寄生电容，可用于进行IP2自检和/或校准的内部环回导体。在第一个新颖的方面，收发器的发射混频器是电流模式输出混频器。接收混频器是具有低输入阻抗的无源混频器。在环回模式下，发射混频器通过环回导体将两声音电流信号驱动到无源混频器。在第二个新颖的方面，发射混频器只有一个正交分支用于产生执行IP2测试所需的两个音调。在第三个新颖的方面，使用发射混频器的一个正交分支进行第一校准测试，同时使用其他正交分支执行第二校准测试，从而减少环回测试时间和功耗。

2. 发明申请

US20130281042A1 RECONFIGURABLE LNA FOR INCREASED JAMMER REJECTION 有权
标题翻译：用于增加JAMMER拒绝的可重构LNA
公开(公告)号：US20130281042A1
公开(公告)日：2013-10-24
申请号：US13450120
申请日：2012-04-18
申请人： Cheng-Han Wang , Liang Zhao , Hong Sun Kim , Jin-Su Ko
发明人： Cheng-Han Wang , Liang Zhao , Hong Sun Kim , Jin-Su Ko
IPC分类号： H04B1/10
CPC分类号： H03F3/45188 , H03F1/565 , H03F3/193 , H03F2200/294 , H03F2200/546 , H03F2203/45386 , H03F2203/45641 , H03F2203/45726 , H04B1/109 , H04B1/3805
摘要： A reconfigurable LNA for increased jammer rejection is disclosed. An exemplary embodiment includes an LNA having a tunable resonant frequency, and a detector configured to output a control signal to tune the resonant frequency of the LNA to increase jammer suppression. An exemplary method includes detecting if a jammer is present, tuning a resonant frequency of an LNA away from the jammer to increase jammer rejection if the jammer is present, and tuning the resonant frequency of the LNA to a selected operating frequency if the jammer is not present.
摘要翻译：公开了一种用于增加干扰抑制的可重构LNA。示例性实施例包括具有可调谐谐振频率的LNA，以及被配置为输出控制信号以调谐LNA的谐振频率以增加干扰抑制的检测器。一种示例性方法包括检测干扰信号是否存在，如果干扰信号存在，则调谐LNA的谐振频率远离干扰信号以增加干扰抑制，并且如果干扰信号不是，则将LNA的谐振频率调谐到所选择的操作频率当下。

3. 发明授权

US07675273B2 Wideband low dropout voltage regulator 失效
标题翻译：宽带低压差稳压器
公开(公告)号：US07675273B2
公开(公告)日：2010-03-09
申请号：US11864364
申请日：2007-09-28
申请人： Jin-Su Ko , Sunghyun Park
发明人： Jin-Su Ko , Sunghyun Park
IPC分类号： G05F1/59 , G05F1/575
CPC分类号： G05F1/575
摘要： A method and apparatus for regulating a supply voltage to an integrated circuit is disclosed. The method and apparatus provides good power supply noise rejection characteristics over a wide bandwidth as well as low dropout voltage. In the disclosed methods and apparatus, native NMOS source followers may be stacked and coupled to a supply rail to supply a regulated voltage to a load. The gates of the native NMOS source followers may be coupled to the outputs of internal regulators. The internal regulators may also contain stacked NMOS source followers. In an embodiment, the internal regulators may be supplied by a high voltage source, while native NMOS source followers may be supplied by a low voltage source. In another embodiment, lo-pass filters may filter the signal from the internal regulators to the NMOS source followers. In yet another embodiment, the gates of the source followers may be coupled to the sources of the transistors with the internal regulators.
摘要翻译：公开了一种用于调节集成电路的电源电压的方法和装置。该方法和装置在宽带宽以及低压降电压下提供良好的电源噪声抑制特性。在所公开的方法和装置中，天然NMOS源极跟随器可以堆叠并耦合到电源轨，以向负载提供调节电压。天然NMOS源极跟随器的栅极可以耦合到内部稳压器的输出端。内部稳压器也可以包含堆叠的NMOS源极跟随器。在一个实施例中，内部稳压器可以由高电压源提供，而天然NMOS源极跟随器可由低电压源提供。在另一个实施例中，通滤波器可以将来自内部稳压器的信号滤波到NMOS源极跟随器。在又一个实施例中，源极跟随器的栅极可以利用内部稳压器耦合到晶体管的源极。

4. 发明申请

US20100026393A1 DRIVER AMPLIFIER HAVING A PROGRAMMABLE OUTPUT IMPEDANCE ADJUSTMENT CIRCUIT 有权
标题翻译：具有可编程输出阻抗调整电路的驱动放大器
公开(公告)号：US20100026393A1
公开(公告)日：2010-02-04
申请号：US12182403
申请日：2008-07-30
申请人： Arvind Keerti , Jin-Su Ko
发明人： Arvind Keerti , Jin-Su Ko
IPC分类号： H03F1/56
CPC分类号： H03F1/56
摘要： A driver amplifier in an integrated circuit is suitable for driving a signal onto an output node and through an output terminal, and through a matching network to a power amplifier. A novel Programmable Output Impedance Adjustment Circuit (POIAC) within the integrated circuit is coupled to the output node and affects an output impedance looking into the output terminal. When the output impedance would otherwise change (for example, due to a driver amplifier power gain change), the POIAC adjusts how it loads the output node such that the output impedance remains substantially constant. The POIAC uses a series-connected inductor and capacitor L-C-R circuit to load the output node, thereby reducing the amount of capacitance and die area required to perform multi-band impedance matching with a power amplifier. Multi-band operation is accomplished by changing an effective capacitance in the L-C-R circuit depending on communication band information received by the POIAC.
摘要翻译：集成电路中的驱动放大器适用于将信号驱动到输出节点上，并通过输出端，并通过匹配网络到功率放大器。集成电路内的新型可编程输出阻抗调整电路（POIAC）耦合到输出节点并影响输出端子的输出阻抗。当输出阻抗否则会改变（例如，由于驱动器放大器功率增益变化）时，POIAC调整如何加载输出节点，使得输出阻抗基本保持不变。 POIAC使用串联电感器和电容器L-C-R电路来加载输出节点，从而减少与功率放大器执行多频带阻抗匹配所需的电容量和管芯面积。通过根据POIAC接收的通信频带信息改变L-C-R电路中的有效电容来实现多频带操作。

5. 发明授权

US08170506B2 Direct current (DC) offset correction using analog-to-digital conversion 失效
标题翻译：使用模数转换的直流（DC）偏移校正
公开(公告)号：US08170506B2
公开(公告)日：2012-05-01
申请号：US12181904
申请日：2008-07-29
申请人： Bahman Ahrari , Hee Choul Lee , Jin-Su Ko , Sang Oh Lee
发明人： Bahman Ahrari , Hee Choul Lee , Jin-Su Ko , Sang Oh Lee
IPC分类号： H04B1/04 , H04B17/00
CPC分类号： H04L25/061 , H04L27/364
摘要： Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions. The instructions allow one-shot DC offset correction, instead of successive approximation for DC offset correction.
摘要翻译：公开了用于减少或消除发射机中的DC（直流）偏移的技术。用于DC偏移减小的装置可以包括转换器，数字引擎和多个可编程电流源。转换器被配置为提供分别与多个差分信号支路相关联的多个DC电流的数字表示。数字引擎被配置为接收数字表示并且基于分别在每个数字表示和校准电流之间的比较来产生用于产生用于多个差分信号支路的补偿电流的指令。可编程电流电源分别对应于差分信号支路。当前电源被配置为分别将补偿电流注入到差分信号支路中，以基于指令减小差分信号支路之间的DC偏移。该指令允许单次直流偏移校正，而不是逐次逼近直流偏移校正。

6. 发明申请

US20100026383A1 DIRECT CURRENT (DC) OFFSET CORRECTION USING ANALOG-TO-DIGITAL CONVERSION 失效
标题翻译：使用模拟数字转换的直接电流（DC）偏移校正
公开(公告)号：US20100026383A1
公开(公告)日：2010-02-04
申请号：US12181904
申请日：2008-07-29
申请人： Bahman Ahrari , Hee Choul Lee , Jin-Su Ko , Sang Oh Lee
发明人： Bahman Ahrari , Hee Choul Lee , Jin-Su Ko , Sang Oh Lee
IPC分类号： H04B1/10
CPC分类号： H04L25/061 , H04L27/364
摘要： Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions. The instructions allow one-shot DC offset correction, instead of successive approximation for DC offset correction.
摘要翻译：公开了用于减少或消除发射机中的DC（直流）偏移的技术。用于DC偏移减小的装置可以包括转换器，数字引擎和多个可编程电流源。转换器被配置为提供分别与多个差分信号支路相关联的多个DC电流的数字表示。数字引擎被配置为接收数字表示并且基于分别在每个数字表示和校准电流之间的比较来产生用于产生用于多个差分信号支路的补偿电流的指令。可编程电流电源分别对应于差分信号支路。当前电源被配置为分别将补偿电流注入到差分信号支路中，以基于指令减小差分信号支路之间的DC偏移。该指令允许单次直流偏移校正，而不是逐次逼近直流偏移校正。

7. 发明申请

US20090085534A1 WIDEBAND LOW DROPOUT VOLTAGE REGULATOR 失效
标题翻译：宽带低压差稳压器
公开(公告)号：US20090085534A1
公开(公告)日：2009-04-02
申请号：US11864364
申请日：2007-09-28
申请人： Jin-Su Ko , Sunghyun Park
发明人： Jin-Su Ko , Sunghyun Park
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： Method and apparatus for regulating a supply voltage. Native NMOS source followers may be stacked and coupled to a supply a regulated voltage to a load. The gates of the native NMOS source followers are coupled to the outputs of internal regulators. The internal regulators may also contain stacked NMOS source followers. In an embodiment, the internal regulators may be supplied by a high voltage source, while the native NMOS source followers may be supplied by a low voltage source. In another embodiment, low-pass filters may filter the signal from the internal regulators to the NMOS source followers. In yet another embodiment, the gates of the source followers may be coupled to the sources of the transistors within the internal regulators.
摘要翻译：用于调节电源电压的方法和装置。原生NMOS源极跟随器可以被堆叠并耦合到向负载提供调节电压。天然NMOS源极跟随器的栅极耦合到内部稳压器的输出端。内部稳压器也可以包含堆叠的NMOS源极跟随器。在一个实施例中，内部稳压器可以由高电压源提供，而天然NMOS源极跟随器可由低电压源提供。在另一个实施例中，低通滤波器可以将来自内部稳压器的信号滤波到NMOS源极跟随器。在另一个实施例中，源极跟随器的栅极可以耦合到内部稳压器内的晶体管的源极。

8. 发明申请

US20100120369A1 RF TRANSCEIVER IC HAVING INTERNAL LOOPBACK CONDUCTOR FOR IP2 SELF TEST 有权
标题翻译：具有IP2自检功能的内部回路导线器的射频收发器IC
公开(公告)号：US20100120369A1
公开(公告)日：2010-05-13
申请号：US12270755
申请日：2008-11-13
申请人： Jin-Su Ko , Michael Kohlmann , Bahman Ahrari
发明人： Jin-Su Ko , Michael Kohlmann , Bahman Ahrari
IPC分类号： H04B17/00
CPC分类号： H04B1/40 , H03D7/168
摘要： An RF transceiver integrated circuit has a novel segmented, low parasitic capacitance, internal loopback conductor usable for conducting IP2 self testing and/or calibration. In a first novel aspect, the transmit mixer of the transceiver is a current mode output mixer. The receive mixer is a passive mixer that has a low input impedance. In the loopback mode, the transmit mixer drives a two tone current signal to the passive mixer via the loopback conductor. In a second novel aspect, only one quadrature branch of the transmit mixer is used to generate both tones required for carrying out an IP2 test. In a third novel aspect, a first calibration test is performed using one quadrature branch of the transmit mixer at the same time that a second calibration test is performed using the other quadrature branch, thereby reducing loopback test time and power consumption.
摘要翻译： RF收发器集成电路具有新颖的分段，低寄生电容，可用于进行IP2自检和/或校准的内部环回导体。在第一个新颖的方面，收发器的发射混频器是电流模式输出混频器。接收混频器是具有低输入阻抗的无源混频器。在环回模式下，发射混频器通过环回导体将两声音电流信号驱动到无源混频器。在第二个新颖的方面，发射混频器只有一个正交分支用于产生执行IP2测试所需的两个音调。在第三个新颖的方面，使用发射混频器的一个正交分支进行第一校准测试，同时使用其他正交分支执行第二校准测试，从而减少环回测试时间和功耗。

9. 发明申请

US20100067422A1 APPARATUS AND METHODS FOR CONTROLLING A SLEEP MODE IN A WIRELESS DEVICE 审中-公开
标题翻译：用于控制无线设备中的休眠模式的装置和方法
公开(公告)号：US20100067422A1
公开(公告)日：2010-03-18
申请号：US12557414
申请日：2009-09-10
申请人： Tamer A. Kadous , Michael Kohlmann , Alexei Y. Gorokhov , Jin-Su Ko
发明人： Tamer A. Kadous , Michael Kohlmann , Alexei Y. Gorokhov , Jin-Su Ko
IPC分类号： H04W52/02 , G08C17/00
CPC分类号： H04W52/0229 , Y02D70/122 , Y02D70/1242 , Y02D70/1262 , Y02D70/142 , Y02D70/146 , Y02D70/22
摘要： Apparatus and methods for controlling sleep mode in a wireless device are disclosed. The sleep mode is controlled using low power detection of RF beacon signals of known frequencies to reduce power consumption of the wireless device during sleep modes. Detection is achieved by using passive or low power elements in a receive chain that filters received signals allowing beacon signals of particular frequencies to pass, which are accumulated with passive or low power circuit elements requiring no external power source. The accumulated energy is compared to a threshold to determine the presence of the beacon with sleep circuitry. When the beacon is detected, the full RF receiver is triggered to wake up. Use of low power elements and passive elements, affords a beneficial increase in power savings for the wireless device, which is particularly helpful in wireless access points or relay stations that have an alternative power sourcing such as battery or solar power.
摘要翻译：公开了一种用于在无线设备中控制睡眠模式的装置和方法。使用已知频率的RF信标信号的低功率检测来控制睡眠模式，以减少睡眠模式期间无线设备的功耗。通过在接收链中使用无源或低功率元件来实现检测，该接收链对接收到的信号进行滤波，允许特定频率的信标信号通过，这些信号是不需要外部电源的无源或低功率电路元件。将累积的能量与阈值进行比较以确定具有睡眠电路的信标的存在。当检测到信标时，触发完整的RF接收机唤醒。使用低功率元件和无源元件，为无线设备的功率节省提供了有益的增加，这在具有替代电源（例如电池或太阳能）的无线接入点或中继站中特别有用。

10. 发明授权

US06426678B1 High power amplifier system having low power consumption and high dynamic range 有权
标题翻译：高功率放大器系统具有低功耗和高动态范围
公开(公告)号：US06426678B1
公开(公告)日：2002-07-30
申请号：US09930345
申请日：2001-08-15
申请人： Jin-su Ko
发明人： Jin-su Ko
IPC分类号： H03F304
CPC分类号： H03F1/0266
摘要： A high power amplifier system having low electric power consumption and a high dynamic range is provided. The high power amplifier system receives at least one control signal for enabling selection of the maximum current and the minimum current, reference voltage, control voltage for controlling gain and an input signal and then selects the maximum and minimum currents in response to at least one control signal. If the control voltage for controlling gain, that is, the gain of an output signal with respect to an input signal has a high voltage value within a range between the maximum current and the minimum current, the high power amplifier system magnifies the amount of current flowing in an amplification circuit therein. If the control voltage for controlling gain, that is, the gain of an output signal with respect to an input signal is low, the high power amplifier system reduces the amount of current flowing in the amplification circuit. As a result, the high power amplifier system keeps a high dynamic range within a predetermined voltage range of the control voltage and enables a particular amount of current to flow in case the control voltage is over the predetermined voltage range, thereby minimizing the amount of current flowing therein.
摘要翻译：提供了具有低功耗和高动态范围的高功率放大器系统。高功率放大器系统接收至少一个控制信号，以便能够选择最大电流和最小电流，参考电压，用于控制增益的控制电压和输入信号，然后响应于至少一个控制选择最大和最小电流信号。如果用于控制增益的控制电压（即，相对于输入信号的输出信号的增益）在最大电流和最小电流之间的范围内具有高电压值，则高功率放大器系统放大电流量在其中的放大电路中流动。如果用于控制增益的控制电压，即输出信号相对于输入信号的增益为低，则高功率放大器系统减少在放大电路中流动的电流量。结果，高功率放大器系统在控制电压的预定电压范围内保持高动态范围，并且在控制电压超过预定电压范围的情况下使特定电流量流动，从而最小化电流量流入其中

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