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1. 发明授权

US08984249B2 ID generation apparatus and method for serially interconnected devices 有权
标题翻译：用于串行互连设备的ID产生设备和方法
公开(公告)号：US08984249B2
公开(公告)日：2015-03-17
申请号：US11613563
申请日：2006-12-20
申请人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Steven Przybylski
发明人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Steven Przybylski
IPC分类号： G06F12/00 , G11C7/20 , G06F13/42 , G11C7/10 , G11C19/00 , G11C29/44
CPC分类号： G11C7/20 , G06F13/4291 , G11C7/10 , G11C7/1003 , G11C19/00 , G11C2029/4402
摘要： A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.
摘要翻译：多个存储器件（例如，DRAM，SRAM，NAND闪存，NOR闪存）被串联连接。每个互连设备接收设备标识符（ID）并将其锁定为其ID。每个设备包括用于计算另一个ID或增加的ID以生成它的电路。生成的ID被传送到另一个设备，并且ID在串行互连中的每个设备中增加。互连中的最后一个设备提供最后生成的ID，其提供给具有从所提供的最后生成的ID识别串行互连设备的总数的识别电路的存储器控制器。识别电路识别串行互连中设备的总输出延迟。

2. 发明授权

US08407395B2 Scalable memory system 失效
标题翻译：可扩展内存系统
公开(公告)号：US08407395B2
公开(公告)日：2013-03-26
申请号：US11843440
申请日：2007-08-22
申请人： Jin-Ki Kim , HakJune Oh , Hong Beom Pyeon , Steven Przybylski
发明人： Jin-Ki Kim , HakJune Oh , Hong Beom Pyeon , Steven Przybylski
IPC分类号： G06F12/00
CPC分类号： G11C7/1042 , G06F12/0623 , G06F13/1694 , G06F13/4256 , G11C7/10 , G11C7/22 , G11C16/06 , G11C16/10 , G11C2216/30 , Y02D10/14 , Y02D10/151
摘要： A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.
摘要翻译：存储器系统架构具有串行连接的存储器件。内存系统具有可扩展性，可以包含任何数量的内存设备，而不会造成任何性能下降或重新设计。每个存储器件具有用于在其他存储器件和存储器控制器之间进行通信的串行输入/输出接口。存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。

3. 发明授权

US08363444B2 Bridge device architecture for connecting discrete memory devices to a system 有权
标题翻译：用于将分立存储器件连接到系统的桥接器件架构
公开(公告)号：US08363444B2
公开(公告)日：2013-01-29
申请号：US13365895
申请日：2012-02-03
申请人： Jin-Ki Kim , HakJune Oh , Hong Beom Pyeon
发明人： Jin-Ki Kim , HakJune Oh , Hong Beom Pyeon
IPC分类号： G11C7/02
CPC分类号： G11C5/02 , G06F13/4234 , G06F13/4247 , G11C5/04 , G11C7/10 , G11C7/1003 , H01L2224/48145 , H01L2224/48227 , H01L2924/15311
摘要： A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at least one discrete memory device, a local input/output interface for connecting to the at least one discrete memory device, and a global input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.
摘要翻译：用于连接分立存储器件的桥接器件架构。桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。桥接器件包括用于连接至少一个分立存储器件的本地控制接口，用于连接至少一个分立存储器件的本地输入/输出接口以及全局输入/输出接口。全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

4. 发明授权

US08060691B2 Apparatus and method of page program operation for memory devices with mirror back-up of data 失效
标题翻译：具有镜像备份数据的存储器件的页面编程操作的装置和方法
公开(公告)号：US08060691B2
公开(公告)日：2011-11-15
申请号：US13022166
申请日：2011-02-07
申请人： Hong Beom Pyeon , Jin-Ki Kim , HakJune Oh
发明人： Hong Beom Pyeon , Jin-Ki Kim , HakJune Oh
IPC分类号： G06F13/00 , G06F13/28 , G06F3/00 , G06F5/00
CPC分类号： G06F13/4243 , G06F13/4247
摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.
摘要翻译：提供了一种页面编程操作的装置和方法。当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本。在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

5. 发明授权

US07515471B2 Memory with output control 有权
标题翻译：内存带输出控制
公开(公告)号：US07515471B2
公开(公告)日：2009-04-07
申请号：US11583354
申请日：2006-10-19
申请人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
发明人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G06F1/12 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C2207/107
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
摘要翻译：公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

6. 发明申请

US20080181214A1 APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE 有权
标题翻译：用于生产混合类型的串联互连设备的设备标识符的装置和方法
公开(公告)号：US20080181214A1
公开(公告)日：2008-07-31
申请号：US11692452
申请日：2007-03-28
申请人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
发明人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
IPC分类号： H04L12/56
CPC分类号： G06F13/4243
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the several interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.
摘要翻译：多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。每个设备都有其设备类型的设备类型信息。作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。根据设备类型匹配确定，DT与所生成或接收的ID组合。组合的DT和ID作为传送到下一个设备的分组。在多个互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。参考提供给互连设备的设备类型，依次生成ID。将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。

7. 发明授权

US09183892B2 Data storage and stackable chip configurations 有权
标题翻译：数据存储和堆叠芯片配置
公开(公告)号：US09183892B2
公开(公告)日：2015-11-10
申请号：US13765059
申请日：2013-02-12
申请人： HakJune Oh , Jin-Ki Kim , Hong Beom Pyeon
发明人： HakJune Oh , Jin-Ki Kim , Hong Beom Pyeon
IPC分类号： H01L23/02 , H01L23/34 , H01L23/48 , H01L23/52 , H01L29/40 , G11C5/06 , G11C5/02 , G11C5/04 , H01L25/065
CPC分类号： G11C5/06 , G11C5/02 , G11C5/04 , H01L23/481 , H01L24/73 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/73257 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/01015 , H01L2924/01019 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/20752 , H01L2924/00015
摘要： A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through the memory devices.
摘要翻译：第一存储器件和第二存储器件具有相同的输入/输出布局配置。为了形成堆叠，第二存储器件被固定到第一存储器件。为了便于连接，第二存储器设备相对于堆叠中的第一存储器设备旋转偏移，以使第一存储器件的输出与第二存储器件的相应输入相对准。第二存储器件相对于第一存储器件的旋转偏移将第一存储器件的一个或多个输出与第二存储器件的一个或多个相应的输入对准。基于输出之间的链路和堆叠中的一个存储设备到另一存储设备的输入，存储器设备堆叠可以包括便于通过存储器设备的一个或多个串联连接配置的路径。

8. 发明申请

US20130182485A1 Data Storage and Stackable Configurations 有权
标题翻译：数据存储和可堆叠配置
公开(公告)号：US20130182485A1
公开(公告)日：2013-07-18
申请号：US13765059
申请日：2013-02-12
申请人： HakJune Oh , Jin-Ki Kim , Hong Beom Pyeon
发明人： HakJune Oh , Jin-Ki Kim , Hong Beom Pyeon
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C5/02 , G11C5/04 , H01L23/481 , H01L24/73 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/73257 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06565 , H01L2924/01015 , H01L2924/01019 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/20752 , H01L2924/00015
摘要： A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through the memory devices.
摘要翻译：第一存储器件和第二存储器件具有相同的输入/输出布局配置。为了形成堆栈，第二存储器件被固定到第一存储器件。为了便于连接，第二存储器设备相对于堆叠中的第一存储器设备旋转偏移，以使第一存储器件的输出与第二存储器件的相应输入相对准。第二存储器件相对于第一存储器件的旋转偏移将第一存储器件的一个或多个输出与第二存储器件的一个或多个相应的输入对准。基于输出之间的链路和堆叠中的一个存储设备到另一存储设备的输入，存储器设备堆叠可以包括便于通过存储器设备的一个或多个串联连接配置的路径。

9. 发明授权

US07925854B2 System and method of operating memory devices of mixed type 有权
标题翻译：操作混合型存储器件的系统和方法
公开(公告)号：US07925854B2
公开(公告)日：2011-04-12
申请号：US11771241
申请日：2007-06-29
申请人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
发明人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
IPC分类号： G06F12/00
CPC分类号： G06F13/4239 , G11C16/08 , G11C16/20 , G11C2216/30
摘要： A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.
摘要翻译：提供了存储器系统结构，其中存储器控制器控制串行互连配置中的存储器件。存储器控制器具有用于发送存储器命令的输出端口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入端口。每个存储器件包括诸如NAND型闪存，NOR型闪速存储器，随机存取存储器和静态随机存取存储器之类的存储器。每个存储器命令特定于目标存储器件的存储器类型。存储器命令和存储器响应的数据路径由互连提供。给定的存储器命令遍历存储器件以达到其串行互连配置的预期存储器件。在其接收时，预期的存储器件执行给定的存储器命令，并且如果适当的话，向下一个存储器件发送存储器响应。存储器响应被传送到存储器控制器。

10. 发明授权

US07904639B2 Modular command structure for memory and memory system 有权
标题翻译：内存和内存系统的模块化命令结构
公开(公告)号：US07904639B2
公开(公告)日：2011-03-08
申请号：US11840692
申请日：2007-08-17
申请人： Jin-Ki Kim , HakJune Oh , Hong Beom Pyeon
发明人： Jin-Ki Kim , HakJune Oh , Hong Beom Pyeon
IPC分类号： G06F12/00
CPC分类号： G11C7/1045 , G06F13/1678 , G11C7/10 , Y02D10/14
摘要： A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.
摘要翻译：包括存储器系统和存储器控制器的系统连接到主机系统。存储器系统具有存储数据的至少一个存储器件。控制器将来自主机系统的请求转换成由至少一个存储设备可解释的一个或多个可分离命令。每个命令具有模块化结构，其包括用于至少一个存储器设备中的一个的地址标识符和表示由至少一个存储器设备之一执行的操作的命令标识符。至少一个存储器设备和控制器处于用于通信的串联连接配置中，使得仅一个存储器设备与控制器通信以输入到存储器系统中。存储器系统可以包括连接到公共总线的多个存储器件。

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