专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120276745A1 METHOD FOR FABRICATING HOLE PATTERN IN SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于在半导体器件中制作孔型的方法
公开(公告)号：US20120276745A1
公开(公告)日：2012-11-01
申请号：US13331064
申请日：2011-12-20
申请人： Jin-Ki JUNG , Jung-Hee Park
发明人： Jin-Ki JUNG , Jung-Hee Park
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L28/92
摘要： A method for fabricating a hole pattern in a semiconductor device includes forming a first organic layer over an etch layer, forming a first inorganic layer pattern over the first organic layer, etching the first organic layer using the first inorganic layer pattern as an etching barrier, forming a second organic layer over the first organic layer, forming a second inorganic layer pattern over the second organic layer, where the second inorganic layer pattern crosses the first inorganic pattern, etching the first and second organic layers using the second inorganic layer pattern as an etching barrier, and etching the etch layer using the etched first and second organic layers as an etch barrier to form a hole pattern.
摘要翻译：在半导体器件中制造孔图案的方法包括在蚀刻层上形成第一有机层，在第一有机层上形成第一无机层图案，使用第一无机层图案作为蚀刻阻挡层蚀刻第一有机层，在所述第一有机层上形成第二有机层，在所述第二有机层上形成第二无机层图案，其中所述第二无机层图案与所述第一无机图案交叉，使用所述第二无机层图案蚀刻所述第一和第二有机层作为蚀刻阻挡层，以及使用蚀刻的第一和第二有机层作为蚀刻阻挡层蚀刻蚀刻层以形成孔图案。

2. 发明授权

US08049196B2 Phase-change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US08049196B2
公开(公告)日：2011-11-01
申请号：US12334385
申请日：2008-12-12
申请人： Jin-Ki Jung
发明人： Jin-Ki Jung
IPC分类号： H01L45/00
CPC分类号： H01L45/143 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/126 , H01L45/144
摘要： A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure.
摘要翻译：相变存储器件包括下电极; 以及共享下电极的至少两个相变存储单元。另一相变存储器件包括与相变材料层具有较小接触面积和与PN二极管结构较大接触面积的加热层。

3. 发明申请

US20110256354A1 MASK LAYOUT AND METHOD FOR FORMING VERTICAL CHANNEL TRANSISTOR IN SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：使用其形成半导体器件中的垂直通道晶体管的掩模布局和方法
公开(公告)号：US20110256354A1
公开(公告)日：2011-10-20
申请号：US13173389
申请日：2011-06-30
申请人： Jin-Ki JUNG
发明人： Jin-Ki JUNG
IPC分类号： B32B3/00
CPC分类号： H01L27/10876 , Y10T428/24479
摘要： A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction.
摘要翻译：一种在半导体存储器件中形成垂直沟道晶体管的方法包括：在衬底上形成多个柱，使得多个柱沿第一方向和与第一方向交叉的第二方向布置，支柱在其上具有硬掩模图案; 形成绝缘层以填充柱之间的区域; 在包括所述绝缘层的合成结构上形成掩模图案，其中所述掩模图案具有在第一方向上暴露每两个相邻柱之间的间隙的开口; 使用掩模图案作为蚀刻阻挡层将绝缘层蚀刻到预定深度以形成沟槽; 并用导电材料填充沟槽以形成沿第一方向延伸的字线。

4. 发明申请

US20110110581A1 3D OBJECT RECOGNITION SYSTEM AND METHOD 审中-公开
标题翻译： 3D对象识别系统和方法
公开(公告)号：US20110110581A1
公开(公告)日：2011-05-12
申请号：US12912211
申请日：2010-10-26
申请人： Hyun Seung YANG , Kyu Sung CHO , Jae Sang YOO , Jin Ki JUNG
发明人： Hyun Seung YANG , Kyu Sung CHO , Jae Sang YOO , Jin Ki JUNG
IPC分类号： G06K9/00
CPC分类号： G06K9/00201 , G06K9/469 , G06K9/6211 , G06K9/6278
摘要： Disclosed herein is a three-dimensional (3D) object recognition system and method. The 3D object recognition system includes a storage unit for storing an extended randomized forest in which a plurality of randomized trees is included and each of the randomized trees includes a plurality of leaf nodes, training means for extracting a plurality of keypoints from a training target object image, and calculating and storing an object recognition posterior probability distribution and training target object-based keypoint matching posterior probability distributions, and matching means for extracting a plurality of keypoints from a matching target object image, matching the extracted keypoints to a plurality of leaf nodes, recognizing an object using the object recognition posterior probability distributions, and matching the keypoints to keypoints of the recognized object using training target object-based keypoint matching posterior probability distributions stored at the matched leaf nodes.
摘要翻译：本文公开了三维（3D）对象识别系统和方法。 3D对象识别系统包括存储单元，用于存储其中包括多个随机化树的扩展随机林，并且每个随机化树包括多个叶节点;训练装置，用于从训练对象对象中提取多个关键点图像，以及计算和存储对象识别后验概率分布和训练目标对象的关键点匹配后验概率分布，以及匹配装置，用于从匹配的目标对象图像中提取多个关键点，将提取的关键点与多个叶节点匹配使用对象识别后验概率分布识别对象，并且使用存储在匹配叶节点处的训练目标基于对象的关键点匹配后验概率分布来将关键点与识别对象的关键点进行匹配。

5. 发明申请

US20110076851A1 METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE 失效
标题翻译：用于在半导体器件中制作精细图案的方法
公开(公告)号：US20110076851A1
公开(公告)日：2011-03-31
申请号：US12962307
申请日：2010-12-07
申请人： Jin-Ki JUNG
发明人： Jin-Ki JUNG
IPC分类号： H01L21/3065
CPC分类号： H01L21/265 , H01L21/0273 , H01L21/31138 , H01L21/31144 , Y10S438/924
摘要： A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier.
摘要翻译：在半导体器件中制造精细图案的方法包括在其上形成蚀刻目标层的衬底上形成第一光致抗蚀剂，将选自元素周期表的III族元素和V族元素中的至少一种杂质掺杂到第一光致抗蚀剂，在第一光致抗蚀剂上形成光致抗蚀剂图案，使用光致抗蚀剂图案进行干蚀刻工艺以暴露第一光致抗蚀剂，通过氧基干蚀刻蚀刻第一光致抗蚀剂以形成掺杂区域被氧化的第一光致抗蚀剂图案，并使用第一光致抗蚀剂图案作为蚀刻阻挡层蚀刻蚀刻目标层。

6. 发明申请

US20100062581A1 METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20100062581A1
公开(公告)日：2010-03-11
申请号：US12432187
申请日：2009-04-29
申请人： Jung-Woo PARK , Jin-Ki JUNG , Kwon HONG , Ki-Seon PARK
发明人： Jung-Woo PARK , Jin-Ki JUNG , Kwon HONG , Ki-Seon PARK
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L27/11519 , H01L27/11521
摘要： Provided is a method of fabricating a non-volatile semiconductor device. The method includes: forming a first hard mask layer over a substrate; etching the first hard mask layer and the substrate to form a plurality of isolation trenches extending in parallel to one another in a first direction; burying a dielectric layer in the isolation trenches to form a isolation layer; forming a plurality of floating gate mask patterns extending in parallel to one another in a second direction intersecting with the first direction over a resulting structure where the isolation layer is formed; etching the first hard mask layer by using the floating gate mask patterns as an etch barrier to form a plurality of island-shaped floating gate electrode trenches; and burying a conductive layer in the floating gate electrode trenches to form a plurality of island-shaped floating gate electrodes.
摘要翻译：提供了制造非易失性半导体器件的方法。该方法包括：在衬底上形成第一硬掩模层; 蚀刻第一硬掩模层和衬底以形成在第一方向上彼此平行延伸的多个隔离沟槽; 在隔离沟槽中埋置介电层以形成隔离层; 在形成所述隔离层的结果上形成在与所述第一方向相交的第二方向上彼此平行延伸的多个浮置栅极掩模图案; 通过使用浮栅掩模图案作为蚀刻势垒来蚀刻第一硬掩模层，以形成多个岛状浮栅电极沟槽; 并在所述浮栅电极沟槽中埋设导电层以形成多个岛状浮栅。

7. 发明申请

US20090162794A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20090162794A1
公开(公告)日：2009-06-25
申请号：US12165407
申请日：2008-06-30
申请人： Jin-Ki JUNG
发明人： Jin-Ki JUNG
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/31144
摘要： A method for fabricating a semiconductor device is provided. The method includes forming an even number of first hard mask patterns over an etch target layer, forming sacrificial patterns on sidewalls of the first hard mask patterns and forming second hard mask patterns on sidewalls of the sacrificial patterns. The second hard mask patterns are formed to have a first space between the first hard mask patterns. The etch target layer is etched by using the first and the second hard mask patterns.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在蚀刻目标层上形成偶数个第一硬掩模图案，在第一硬掩模图案的侧壁上形成牺牲图案，并在牺牲图案的侧壁上形成第二硬掩模图案。形成第二硬掩模图案以在第一硬掩模图案之间具有第一空间。通过使用第一和第二硬掩模图案蚀刻蚀刻目标层。

8. 发明授权

US07527986B1 Method for fabricating magnetic tunnel junction cell 有权
标题翻译：制造磁性隧道结电池的方法
公开(公告)号：US07527986B1
公开(公告)日：2009-05-05
申请号：US12165368
申请日：2008-06-30
申请人： Jin-Ki Jung
发明人： Jin-Ki Jung
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , G11C11/161
摘要： A method for fabricating a magnetic tunnel junction cell comprises forming an insulation layer with an opening, forming a first pattern including multiple layers of a first electrode pattern on a bottom surface and a sidewall of the opening and an anti-ferromagnetic pattern over the first electrode pattern, forming a magnetic tunnel junction layer over the first pattern and the insulation layer, forming a second electrode having a line width greater than the width of the opening, over the magnetic tunnel junction layer, and etching the magnetic tunnel junction layer using the second electrode as an etch barrier.
摘要翻译：制造磁性隧道结单元的方法包括：形成具有开口的绝缘层，在该第一电极的底表面和侧壁上形成包括第一电极图案的多层的第一图案和反铁磁图案在所述第一图案和所述绝缘层上形成磁性隧道结层，在所述磁性隧道结层上形成具有大于所述开口的宽度的线宽的第二电极，并且使用所述第二电极蚀刻所述磁性隧道结层电极作为蚀刻阻挡层。

9. 发明授权

US07018930B2 Method for fabricating semiconductor device 失效
公开(公告)号：US07018930B2
公开(公告)日：2006-03-28
申请号：US10292540
申请日：2002-11-12
申请人： Sung-Kwon Lee , Sang-Ik Kim , Il-Young Kwon , Kuk-Han Yoon , Phil-Goo Kong , Jin-Sung Oh , Jin-Ki Jung , Jae-Young Kim , Kwang-Ok Kim , Myung-Kyu Ahn
发明人： Sung-Kwon Lee , Sang-Ik Kim , Il-Young Kwon , Kuk-Han Yoon , Phil-Goo Kong , Jin-Sung Oh , Jin-Ki Jung , Jae-Young Kim , Kwang-Ok Kim , Myung-Kyu Ahn
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： A method for fabricating a semiconductor device capable of minimizing deformations of a photoresist pattern and losses of a hard mask. The method includes the steps of: forming an insulating layer for a hard mask on an etch-target layer; forming a sacrificial layer on the insulating layer; forming a photoresist pattern on the sacrificial layer; forming at least one sacrificial hard mask by etching the sacrificial layer with the photoresist pattern as an etching mask; forming the hard mask by etching the insulating layer with the sacrificial hard mask as an etching mask; and forming a predetermined number of patterns by etching the etch-target layer with use of the sacrificial hard mask and the hard mask as etching masks.

10. 发明授权

US08491799B2 Method for forming magnetic tunnel junction cell 有权
标题翻译：形成磁性隧道结电池的方法
公开(公告)号：US08491799B2
公开(公告)日：2013-07-23
申请号：US12165363
申请日：2008-06-30
申请人： Jin-Ki Jung
发明人： Jin-Ki Jung
IPC分类号： B44C1/22
CPC分类号： H01L43/12 , G11C11/161
摘要： A method for forming a magnetic tunnel junction cell includes forming a pinning layer, a pinned layer, a dielectric layer and a free layer over a first electrode, forming a second electrode on the free layer, etching the free layer and the dielectric layer using the second electrode as an etch barrier to form a first pattern, forming a prevention layer on a sidewall of the first pattern, and etching the pinned layer and the pinning layer using the second electrode and the prevention layer as an etch barrier to form a second pattern.
摘要翻译：形成磁性隧道结电池的方法包括在第一电极上形成钉扎层，钉扎层，电介质层和自由层，在自由层上形成第二电极，使用第二电极作为蚀刻阻挡层以形成第一图案，在第一图案的侧壁上形成防止层，并且使用第二电极和防止层蚀刻被钉扎层和钉扎层作为蚀刻阻挡层以形成第二图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式