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1. 发明申请

US20130337652A1 MASK PATTERN FOR HOLE PATTERNING AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：用于孔型图案的掩模图案及使用其制造半导体器件的方法
公开(公告)号：US20130337652A1
公开(公告)日：2013-12-19
申请号：US13607898
申请日：2012-09-10
申请人： Jun-Hyeub SUN , Sung-Kwon Lee , Sang-Oh Lee
发明人： Jun-Hyeub SUN , Sung-Kwon Lee , Sang-Oh Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/67063 , G03F1/00 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L27/10852 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns.
摘要翻译：一种制造半导体器件的方法包括在包括第一区域和第二区域的衬底上形成蚀刻目标层; 在蚀刻目标层上形成硬掩模层; 在所述硬掩模层上形成第一蚀刻掩模，其中所述第一蚀刻掩模包括多个线图案和形成在所述线图案上的牺牲间隔层; 在所述第一蚀刻掩模上形成第二蚀刻掩模，其中所述第二蚀刻掩模包括网状图案和覆盖所述第二区域的阻挡图案; 去除牺牲间隔层; 通过使用第二蚀刻掩模和第一蚀刻掩模蚀刻硬掩模层来形成具有多个孔的硬掩模层图案; 以及通过使用所述硬掩模层图案蚀刻所述蚀刻目标层，在所述第一区域中形成多个孔图案。

2. 发明授权

US07790546B2 Method for forming storage node of capacitor in semiconductor device 有权
标题翻译：在半导体器件中形成电容器的存储节点的方法
公开(公告)号：US07790546B2
公开(公告)日：2010-09-07
申请号：US12168823
申请日：2008-07-07
申请人： Jun-Hyeub Sun , Sung-Kwon Lee , Sung-Yoon Cho
发明人： Jun-Hyeub Sun , Sung-Kwon Lee , Sung-Yoon Cho
IPC分类号： H01L21/8242
CPC分类号： H01L21/76897 , H01L27/10855 , H01L28/90
摘要： A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact plugs filled into the first contact holes; forming a second insulation layer with a different etch rate from the first insulation layer over the storage-node contact plugs; forming a third insulation layer on the second insulation layer; sequentially etching the third insulation layer and the second insulation layer to form a plurality of second contact holes exposing the storage-node contact plugs; and forming the storage node on each of the second contact holes.
摘要翻译：一种在半导体器件中形成电容器的方法包括在半成品衬底上形成层间层; 蚀刻层间绝缘层以形成多个第一接触孔; 在所述第一接触孔的侧壁上形成第一绝缘层; 形成填充到所述第一接触孔中的多个存储节点接触插塞; 在所述存储节点接触插塞上形成具有与所述第一绝缘层不同的蚀刻速率的第二绝缘层; 在所述第二绝缘层上形成第三绝缘层; 依次蚀刻第三绝缘层和第二绝缘层，以形成暴露存储节点接触插塞的多个第二接触孔; 以及在所述第二接触孔中的每一个上形成所述存储节点。

3. 发明授权

US07714435B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07714435B2
公开(公告)日：2010-05-11
申请号：US12353883
申请日：2009-01-14
申请人： Sung-Kwon Lee , Myung-Ok Kim
发明人： Sung-Kwon Lee , Myung-Ok Kim
IPC分类号： H01L23/48
CPC分类号： H01L29/94 , H01L28/91
摘要： A method for fabricating a three dimensional type capacitor is provided. The method includes forming a first insulation layer including first contact layers over a substrate, forming a second insulation layer over the first insulation layer, forming second contact layers by using a material having an etch selectivity different from the first contact layers such that the second contact layers are connected with the first contact layers within the second insulation layer, forming an etch stop layer over the second insulation layer and the second contact layers, forming a third insulation layer over the etch stop layer, etching the third insulation layer and the etch stop layer to form first contact holes exposing the second contact layers, etching the exposed second contact layers to form second contact holes exposing the first contact holes, and forming bottom electrodes over the inner surface of the second contact holes.
摘要翻译：提供一种制造三维型电容器的方法。该方法包括在衬底上形成包括第一接触层的第一绝缘层，在第一绝缘层上形成第二绝缘层，通过使用具有不同于第一接触层的蚀刻选择性的材料形成第二接触层，使得第二接触层与第二绝缘层内的第一接触层连接，在第二绝缘层和第二接触层上方形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层，蚀刻第三绝缘层和蚀刻停止层以形成暴露第二接触层的第一接触孔，蚀刻暴露的第二接触层以形成暴露第一接触孔的第二接触孔，以及在第二接触孔的内表面上形成底电极。

4. 发明授权

US07700493B2 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07700493B2
公开(公告)日：2010-04-20
申请号：US11904401
申请日：2007-09-27
申请人： Sung-Kwon Lee , Min-Suk Lee
发明人： Sung-Kwon Lee , Min-Suk Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/31144
摘要： A method for fabricating a semiconductor device includes forming a first pattern over a substrate, forming an oxide-based layer over the first pattern, forming a hard mask layer over the oxide-based layer, etching the hard mask layer at a first substrate temperature, and etching the oxide-based layer to form a second pattern, wherein the oxide-based layer is etched at a second substrate temperature which is greater than the first substrate temperature using a gas including fluorine (F) and carbon (C) as a main etch gas.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成第一图案，在第一图案上形成氧化物基层，在氧化物基层上形成硬掩模层，在第一衬底温度下蚀刻硬掩模层，并且蚀刻所述氧化物基层以形成第二图案，其中所述氧化物基层在使用包含氟（F）和碳（C））为主要气体的第二基板温度下蚀刻，所述第二基板温度大于所述第一基板温度蚀刻气体。

5. 发明授权

US07687344B2 Method for fabricating capacitor in semiconductor device 失效
标题翻译：在半导体器件中制造电容器的方法
公开(公告)号：US07687344B2
公开(公告)日：2010-03-30
申请号：US11320235
申请日：2005-12-27
申请人： Sung-Kwon Lee
发明人： Sung-Kwon Lee
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/10855
摘要： A first insulation layer is formed on a substrate structure including an inter-layer insulation layer and a storage node contact plug. The first insulation layer is etched to form a first opening exposing a portion of the storage node contact plug. The first opening is filled with an organic polymer layer. An etch stop layer and a second insulation layer are formed on the organic polymer layer and the first insulation layer. A photoresist pattern is formed on the second insulation layer. The second insulation layer and the etch stop layer are etched to form a second opening exposing a portion of the organic polymer layer. The photoresist pattern and the organic polymer layer are removed, thereby extending a portion of the second opening. A storage node is formed over the extended second opening and the second insulation layer.
摘要翻译：在包括层间绝缘层和存储节点接触插塞的基板结构上形成第一绝缘层。蚀刻第一绝缘层以形成露出存储节点接触插塞的一部分的第一开口。第一开口填充有机聚合物层。在有机聚合物层和第一绝缘层上形成蚀刻停止层和第二绝缘层。在第二绝缘层上形成光刻胶图形。蚀刻第二绝缘层和蚀刻停止层以形成露出部分有机聚合物层的第二开口。去除光致抗蚀剂图案和有机聚合物层，从而延伸第二开口的一部分。存储节点形成在延伸的第二开口和第二绝缘层上。

6. 发明申请

US20090117492A1 METHOD FOR FORMING FINE PATTERN IN SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中形成精细图案的方法
公开(公告)号：US20090117492A1
公开(公告)日：2009-05-07
申请号：US12165401
申请日：2008-06-30
申请人： Sung-Kwon LEE
发明人： Sung-Kwon LEE
IPC分类号： G03F7/20
CPC分类号： G03F7/40 , H01L21/0337 , H01L21/0338
摘要： A method is used in forming a fine pattern in a semiconductor device. The method includes forming an etch target layer; forming a photoresist pattern over the etch target layer; forming a polymer pattern including silicon-oxygen (Si—O) bonds on sidewalls of the photoresist pattern; removing the photoresist pattern; and etching the etch target layer using the polymer pattern as an etch mask.
摘要翻译：一种在半导体器件中形成精细图案的方法。该方法包括形成蚀刻目标层; 在蚀刻目标层上形成光致抗蚀剂图案; 在所述光致抗蚀剂图案的侧壁上形成包括硅 - 氧（Si-O）键的聚合物图案; 去除光致抗蚀剂图案; 并使用聚合物图案作为蚀刻掩模蚀刻蚀刻目标层。

7. 发明授权

US07508029B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07508029B2
公开(公告)日：2009-03-24
申请号：US11706912
申请日：2007-02-13
申请人： Sung-Kwon Lee
发明人： Sung-Kwon Lee
IPC分类号： H01L29/94
CPC分类号： H01L21/76224 , H01L21/823481
摘要： A semiconductor device capable of preventing a bridge generation during performing an etching process to form a plurality of gate structures on a substrate divided into an active region and a field region and an electrical short between a contact plug and the individual gate structure in the field region and a method for fabricating the same are provided. The semiconductor device includes: a substrate provided with an active region and a field region; a field oxide layer formed in the field region in such a way that the field oxide layer is recessed to be lower than a surface of the substrate disposed in the active region; and a plurality of gate structures formed on the field oxide layer and the substrate in the active region.
摘要翻译：一种半导体器件，其能够在执行蚀刻处理期间防止桥接生成，以在分割成有源区域和场区域的基板上形成多个栅极结构，以及在场区域中的接触插塞和各个栅极结构之间的电短路并提供其制造方法。半导体器件包括：具有有源区和场区的衬底; 场场氧化层，其形成在所述场区域中，使得所述场氧化物层凹陷成低于设置在所述有源区域中的所述衬底的表面; 以及形成在有源区域上的场氧化物层和衬底上的多个栅极结构。

8. 发明授权

US07476625B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07476625B2
公开(公告)日：2009-01-13
申请号：US11241098
申请日：2005-09-29
申请人： Sung-Kwon Lee , Dong-Duk Lee
发明人： Sung-Kwon Lee , Dong-Duk Lee
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76897 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L27/10855
摘要： Disclosed is a method for fabricating a semiconductor device. The method includes: forming a first inter-layer insulation layer on a substrate provided with a plurality of cell contact plugs; selectively etching the first inter-layer insulation layer to form a plurality of first contact holes; performing a cleaning process to remove etch residues on lower portions of the first contact holes; forming insulating fences on inner walls of the first contact holes; forming a plurality of bit lines in contact with a group of the cell contact plugs through the respective first contact holes; forming a second inter-layer insulation layer over the plurality of bit lines; planarizing the second inter-layer insulation layer until an upper portion of each of the bit lines is exposed; and selectively etching the second inter-layer insulation layer in alignment with the bit lines, thereby obtaining a plurality of second contact holes.
摘要翻译：公开了半导体器件的制造方法。该方法包括：在设置有多个单元接触插塞的基板上形成第一层间绝缘层; 选择性地蚀刻第一层间绝缘层以形成多个第一接触孔; 执行清洁处理以去除第一接触孔的下部上的蚀刻残留物; 在所述第一接触孔的内壁上形成绝缘栅栏; 通过相应的第一接触孔形成与一组电池接触插塞接触的多个位线; 在所述多个位线上形成第二层间绝缘层; 平面化第二层间绝缘层直到每个位线的上部被暴露; 并且选择性地蚀刻与位线对准的第二层间绝缘层，由此获得多个第二接触孔。

9. 发明授权

US07444447B2 Arrangement, device and method for controlling bus request signal generation 有权
标题翻译：用于控制总线请求信号生成的布置，装置和方法
公开(公告)号：US07444447B2
公开(公告)日：2008-10-28
申请号：US11043947
申请日：2005-01-28
申请人： Chang-Dae Park , Ki-Chul Nam , Sung-Kwon Lee
发明人： Chang-Dae Park , Ki-Chul Nam , Sung-Kwon Lee
IPC分类号： G06F13/36
CPC分类号： G06F13/372
摘要： A device, arrangement and method may control bus request timing to disperse bus access timing, so that adverse effects of concentration-on-bus phenomenon may be avoided. The device may include a bus request signal generating circuit may generate a bus request signal under control of a counter, and a pulse signal generating circuit may generate a pulse signal as a function of a number of times the bus request signal generating circuit has generated a bus request signal and a first threshold value. The device may include a determining circuit and a control circuit. The determining circuit may generate a determination result representing whether a given process period for generating the bus request signal has ended as a function of the pulse signal. The control circuit may control the counter to adjust the process period for generating the bus request signal, based on the determination result.
摘要翻译：装置，布置和方法可以控制总线请求时序以分散总线访问定时，从而可以避免集中对总线现象的不利影响。该设备可以包括总线请求信号发生电路可以在计数器的控制下产生总线请求信号，并且脉冲信号发生电路可以产生作为总线请求信号发生电路产生的次数的函数的脉冲信号总线请求信号和第一阈值。该装置可以包括确定电路和控制电路。确定电路可以产生表示作为脉冲信号的函数的用于产生总线请求信号的给定处理周期是否结束的确定结果。控制电路可以基于确定结果来控制计数器来调整用于生成总线请求信号的处理周期。

10. 发明授权

US07410866B2 Method for forming storage node of capacitor in semiconductor device 有权
标题翻译：在半导体器件中形成电容器的存储节点的方法
公开(公告)号：US07410866B2
公开(公告)日：2008-08-12
申请号：US11204660
申请日：2005-08-15
申请人： Jun-Hyeub Sun , Sung-Kwon Lee , Sung-Yoon Cho
发明人： Jun-Hyeub Sun , Sung-Kwon Lee , Sung-Yoon Cho
IPC分类号： H01L21/8242
CPC分类号： H01L21/76897 , H01L27/10855 , H01L28/90
摘要： A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact plugs filled into the first contact holes; forming a second insulation layer with a different etch rate from the first insulation layer over the storage-node contact plugs; forming a third insulation layer on the second insulation layer; sequentially etching the third insulation layer and the second insulation layer to form a plurality of second contact holes exposing the storage-node contact plugs; and forming the storage node on each of the second contact holes.
摘要翻译：一种在半导体器件中形成电容器的方法包括在半成品衬底上形成层间层; 蚀刻层间绝缘层以形成多个第一接触孔; 在所述第一接触孔的侧壁上形成第一绝缘层; 形成填充到所述第一接触孔中的多个存储节点接触插塞; 在所述存储节点接触插塞上形成具有与所述第一绝缘层不同的蚀刻速率的第二绝缘层; 在所述第二绝缘层上形成第三绝缘层; 依次蚀刻第三绝缘层和第二绝缘层，以形成暴露存储节点接触插塞的多个第二接触孔; 以及在所述第二接触孔中的每一个上形成所述存储节点。

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