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1. 发明授权

US08285919B2 SSD with improved bad block management 有权
标题翻译： SSD具有改进的坏块管理
公开(公告)号：US08285919B2
公开(公告)日：2012-10-09
申请号：US12693826
申请日：2010-01-26
申请人： Jianjun Luo , ChuanJen Tsu
发明人： Jianjun Luo , ChuanJen Tsu
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F11/1068 , G06F2212/1044 , G06F2212/7208
摘要： In some embodiments, a memory controller includes a plurality of processors of a first type and a processor of a second type coupled to the processors of the first type. Each of the plurality of processors of the first type is configured to determine a bad block rate of a memory channel of a solid state memory device to which it is configured to be coupled. The processor of the second type is configured to receive the bad block data rates from each of the plurality of processors of the first type and to report one of a total capacity or a bad block rate of the solid state memory device to a host device. The total capacity and the bad block rate of the solid state memory device are based on the bad block rates received from each of the plurality of processors of the first type.
摘要翻译：在一些实施例中，存储器控制器包括耦合到第一类型的处理器的第一类型的处理器和第二类型的处理器的多个处理器。第一类型的多个处理器中的每一个被配置为确定其被配置为耦合到的固态存储器件的存储器通道的坏块速率。第二类型的处理器被配置为从第一类型的多个处理器中的每一个接收坏块数据速率，并将固态存储器件的总容量或坏块速率中的一个报告给主机设备。固态存储器件的总容量和坏块率基于从第一类型的多个处理器中的每个处理器接收到的坏块速率。

2. 发明申请

US20100122022A1 SSD WITH IMPROVED BAD BLOCK MANAGMENT 有权
标题翻译：具有改进的边框管理的SSD
公开(公告)号：US20100122022A1
公开(公告)日：2010-05-13
申请号：US12693826
申请日：2010-01-26
申请人： Jianjun LUO , ChuanJen TSU
发明人： Jianjun LUO , ChuanJen TSU
IPC分类号： G06F12/00 , G06F12/02 , G06F11/00 , G06F11/16
CPC分类号： G06F12/0246 , G06F11/1068 , G06F2212/1044 , G06F2212/7208
摘要： In some embodiments, a memory controller includes a plurality of processors of a first type and a processor of a second type coupled to the processors of the first type. Each of the plurality of processors of the first type is configured to determine a bad block rate of a memory channel of a solid state memory device to which it is configured to be coupled. The processor of the second type is configured to receive the bad block data rates from each of the plurality of processors of the first type and to report one of a total capacity or a bad block rate of the solid state memory device to a host device. The total capacity and the bad block rate of the solid state memory device are based on the bad block rates received from each of the plurality of processors of the first type.
摘要翻译：在一些实施例中，存储器控制器包括耦合到第一类型的处理器的第一类型的处理器和第二类型的处理器的多个处理器。第一类型的多个处理器中的每一个被配置为确定其被配置为耦合到的固态存储器件的存储器通道的坏块速率。第二类型的处理器被配置为从第一类型的多个处理器中的每一个接收坏块数据速率，并将固态存储器件的总容量或坏块速率中的一个报告给主机设备。固态存储器件的总容量和坏块率基于从第一类型的多个处理器中的每个处理器接收到的坏块速率。

3. 发明授权

US08151038B2 SSD with a channel multiplier 有权
标题翻译： SSD带有通道倍增器
公开(公告)号：US08151038B2
公开(公告)日：2012-04-03
申请号：US12468683
申请日：2009-05-19
申请人： Jianjun Luo , ChuanJen Tsu , Jui Chuan Liang , Minhorng Ko
发明人： Jianjun Luo , ChuanJen Tsu , Jui Chuan Liang , Minhorng Ko
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F3/0613 , G06F3/0658 , G06F3/0688
摘要： An integrated circuit includes a first serial advanced technology attachment (SATA) channel, a plurality of second SATA channels, and a channel multiplier. The first SATA channel is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of SATA channels is configured to be coupled to a respective separate memory device channel. The channel multiplier is configured to couple the first SATA channel to each of the plurality of second SATA channels.
摘要翻译：集成电路包括第一串行高级技术附件（SATA）通道，多个第二SATA通道和通道倍增器。第一SATA通道被配置为耦合到主机设备的相应串行数据总线。多个SATA通道中的每一个被配置为耦合到相应的单独的存储器件通道。信道乘法器被配置为将第一SATA信道耦合到多个第二SATA信道中的每一个。

4. 发明申请

US20090300274A1 SSD WITH DISTRIBUTED PROCESSORS 有权
标题翻译： SSD与分布式处理器
公开(公告)号：US20090300274A1
公开(公告)日：2009-12-03
申请号：US12468748
申请日：2009-05-19
申请人： Jianjun LUO , ChuanJen TSU
发明人： Jianjun LUO , ChuanJen TSU
IPC分类号： G06F12/02 , G06F13/14
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/0658 , G06F3/0688 , G06F11/1068 , G06F2212/7205 , G06F2212/7208 , G11C2211/5641
摘要： In one embodiment, a system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus.
摘要翻译：在一个实施例中，系统包括串行数据总线，第一类型的多个处理器和第二类型的处理器。串行数据总线被配置为耦合到主机设备的相应串行数据总线。第一类型的多个处理器中的每一个耦合到相应的闪存器件。第二类型的处理器被配置为管理第一类型的多个处理器对串行数据总线的访问。

5. 发明授权

US08244961B2 SSD with distributed processors 有权
标题翻译：带分布式处理器的SSD
公开(公告)号：US08244961B2
公开(公告)日：2012-08-14
申请号：US12468748
申请日：2009-05-19
申请人： Jianjun Luo , ChuanJen Tsu
发明人： Jianjun Luo , ChuanJen Tsu
IPC分类号： G06F12/08
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/0658 , G06F3/0688 , G06F11/1068 , G06F2212/7205 , G06F2212/7208 , G11C2211/5641
摘要： In one embodiment, a system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus.
摘要翻译：在一个实施例中，系统包括串行数据总线，第一类型的多个处理器和第二类型的处理器。串行数据总线被配置为耦合到主机设备的相应串行数据总线。第一类型的多个处理器中的每一个耦合到相应的闪存器件。第二类型的处理器被配置为管理第一类型的多个处理器对串行数据总线的访问。

6. 发明授权

US07970978B2 SSD with SATA and USB interfaces 有权
标题翻译： SSD与SATA和USB接口
公开(公告)号：US07970978B2
公开(公告)日：2011-06-28
申请号：US12468786
申请日：2009-05-19
申请人： Jianjun Luo , ChuanJen Tsu , Minhorng Ko
发明人： Jianjun Luo , ChuanJen Tsu , Minhorng Ko
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/385
摘要： In one embodiment, a data storage system, includes a controller and a plurality of solid state memory devices each including at least one memory unit. The controller includes a data interface of a first type, a data interface of a second type, and a first serial data bus. Each of the data interfaces of the first and second types is configured to be coupled to a corresponding data interface of a host device. The first serial data bus is coupled to each of the data interfaces of the first and second types and to the plurality of solid state memory devices. The controller is configured to manage data flow between the plurality of solid state memory devices and the host device through the data interfaces of the first and second types.
摘要翻译：在一个实施例中，数据存储系统包括控制器和多个固态存储器件，每个固态存储器件包括至少一个存储器单元。控制器包括第一类型的数据接口，第二类型的数据接口和第一串行数据总线。第一类型和第二类型的每个数据接口被配置为耦合到主机设备的相应数据接口。第一串行数据总线耦合到第一类型和第二类型的数据接口以及多个固态存储器件。所述控制器被配置为通过所述第一类型和第二类型的数据接口来管理所述多个固态存储设备与所述主机设备之间的数据流。

7. 发明申请

US20090300259A1 SSD WITH SATA AND USB INTERFACES 有权
标题翻译： SSD与SATA和USB接口
公开(公告)号：US20090300259A1
公开(公告)日：2009-12-03
申请号：US12468786
申请日：2009-05-19
申请人： Jianjun LUO , ChuanJen TSU , Minhorng KO
发明人： Jianjun LUO , ChuanJen TSU , Minhorng KO
IPC分类号： G06F13/20 , G06F12/02
CPC分类号： G06F13/385
摘要： In one embodiment, a data storage system, includes a controller and a plurality of solid state memory devices each including at least one memory unit. The controller includes a data interface of a first type, a data interface of a second type, and a first serial data bus. Each of the data interfaces of the first and second types is configured to be coupled to a corresponding data interface of a host device. The first serial data bus is coupled to each of the data interfaces of the first and second types and to the plurality of solid state memory devices. The controller is configured to manage data flow between the plurality of solid state memory devices and the host device through the data interfaces of the first and second types.
摘要翻译：在一个实施例中，数据存储系统包括控制器和多个固态存储器件，每个固态存储器件包括至少一个存储器单元。控制器包括第一类型的数据接口，第二类型的数据接口和第一串行数据总线。第一类型和第二类型的每个数据接口被配置为耦合到主机设备的相应数据接口。第一串行数据总线耦合到第一类型和第二类型的数据接口以及多个固态存储器件。所述控制器被配置为通过所述第一类型和第二类型的数据接口来管理所述多个固态存储设备与所述主机设备之间的数据流。

8. 发明申请

US20090300258A1 SSD WITH A CHANNEL MULTIPLIER 有权
标题翻译：带通道乘法器的SSD
公开(公告)号：US20090300258A1
公开(公告)日：2009-12-03
申请号：US12468683
申请日：2009-05-19
申请人： Jianjun LUO , ChuanJen TSU , Jui Chuan LIANG , Minhorng KO
发明人： Jianjun LUO , ChuanJen TSU , Jui Chuan LIANG , Minhorng KO
IPC分类号： G06F13/20 , G06F12/02
CPC分类号： G06F13/1684 , G06F3/0613 , G06F3/0658 , G06F3/0688
摘要： An integrated circuit includes a first serial advanced technology attachment (SATA) channel, a plurality of second SATA channels, and a channel multiplier. The first SATA channel is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of SATA channels is configured to be coupled to a respective separate memory device channel. The channel multiplier is configured to couple the first SATA channel to each of the plurality of second SATA channels.
摘要翻译：集成电路包括第一串行高级技术附件（SATA）通道，多个第二SATA通道和通道倍增器。第一SATA通道被配置为耦合到主机设备的相应串行数据总线。多个SATA通道中的每一个被配置为耦合到相应的单独的存储器件通道。信道乘法器被配置为将第一SATA信道耦合到多个第二SATA信道中的每一个。

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