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    • 1. 发明申请
    • PROGRAM METHOD OF NONVOLATILE MEMORY DEVICE
    • 非易失性存储器件的程序方法
    • US20120294087A1
    • 2012-11-22
    • US13238731
    • 2011-09-21
    • Ji-Hyun SEOByong-Kook KIMSung-Jae CHUNG
    • Ji-Hyun SEOByong-Kook KIMSung-Jae CHUNG
    • G11C16/10
    • G11C16/10G11C16/0483
    • A program method of a nonvolatile memory device includes applying a program voltage to a selected word line, applying a first pass voltage to at least one word line adjacent to the selected word line, applying at least one first middle voltage lower than the first pass voltage but higher than an isolation voltage to at least one word line adjacent to the word line receiving the first pass voltage, applying the isolation voltage to a word line adjacent to the word line receiving the first middle voltage, applying at least one second middle voltage higher than the isolation voltage but lower than a second pass voltage to at least one word line adjacent to the word line receiving the isolation voltage, and applying a second pass voltage to at least one word line adjacent to the word line receiving the second middle voltage.
    • 一种非易失性存储装置的编程方法包括对所选择的字线施加编程电压,向与所选字线相邻的至少一个字线施加第一通过电压,施加低于第一通过电压的至少一个第一中间电压 但是高于与接收第一通过电压的字线相邻的至少一个字线的隔离电压,将隔离电压施加到与接收第一中间电压的字线相邻的字线,施加至少一个第二中间电压 比对接收到隔离电压的字线相邻的至少一个字线低的第二通过电压,但是对接收到第二中间电压的字线的至少一个字线施加第二通过电压。
    • 3. 发明授权
    • Program method of nonvolatile memory device
    • 非易失性存储器件的编程方法
    • US08520438B2
    • 2013-08-27
    • US13238731
    • 2011-09-21
    • Ji-Hyun SeoByong-Kook KimSung-Jae Chung
    • Ji-Hyun SeoByong-Kook KimSung-Jae Chung
    • G11C11/34
    • G11C16/10G11C16/0483
    • A program method of a nonvolatile memory device includes applying a program voltage to a selected word line, applying a first pass voltage to at least one word line adjacent to the selected word line, applying at least one first middle voltage lower than the first pass voltage but higher than an isolation voltage to at least one word line adjacent to the word line receiving the first pass voltage, applying the isolation voltage to a word line adjacent to the word line receiving the first middle voltage, applying at least one second middle voltage higher than the isolation voltage but lower than a second pass voltage to at least one word line adjacent to the word line receiving the isolation voltage, and applying a second pass voltage to at least one word line adjacent to the word line receiving the second middle voltage.
    • 一种非易失性存储装置的编程方法包括对所选择的字线施加编程电压,向与所选字线相邻的至少一个字线施加第一通过电压,施加低于第一通过电压的至少一个第一中间电压 但是高于与接收第一通过电压的字线相邻的至少一个字线的隔离电压,将隔离电压施加到与接收第一中间电压的字线相邻的字线,施加至少一个第二中间电压 比对接收到隔离电压的字线相邻的至少一个字线低的第二通过电压,但是对接收到第二中间电压的字线的至少一个字线施加第二通过电压。
    • 5. 发明申请
    • Method of Fabricating Flash Memory Device
    • 制造闪存设备的方法
    • US20090029523A1
    • 2009-01-29
    • US12179448
    • 2008-07-24
    • Ji Hyun SeoSeok Pyo SongDong Sun Sheen
    • Ji Hyun SeoSeok Pyo SongDong Sun Sheen
    • H01L21/762
    • H01L21/3081H01L21/3086H01L21/31111H01L21/31116H01L21/76232H01L27/11521
    • The invention relates to a method of fabricating flash memory device. In accordance with an aspect of the invention, the method includes forming a gate insulating layer, a first conductive layer, and an isolation mask over a semiconductor substrate. The isolation mask is patterned to expose regions in which an isolation layer will be formed. The first conductive layer, the gate insulating layer, and the semiconductor substrate are etched using the patterned isolation mask to form trenches. A liner oxide layer is formed on the resulting structure including the trenches. The trenches in which the liner oxide layer is formed are filled with an insulating layer. A planarizing process and a cleaning process are carried out such that wing spacers covering the gate insulating layer are formed at top edge portions of the isolation layer, thereby forming the isolation layer.
    • 本发明涉及一种制造闪速存储器件的方法。 根据本发明的一个方面,所述方法包括在半导体衬底上形成栅绝缘层,第一导电层和隔离掩模。 隔离掩模被图案化以暴露其中将形成隔离层的区域。 使用图案化隔离掩模蚀刻第一导电层,栅极绝缘层和半导体衬底,以形成沟槽。 在包括沟槽的所得结构上形成衬里氧化物层。 形成衬垫氧化物层的沟槽填充有绝缘层。 执行平面化处理和清洁处理,使得覆盖栅绝缘层的翼间隔件形成在隔离层的顶部边缘部分,从而形成隔离层。
    • 6. 发明申请
    • Method of Manufacturing Semiconductor Device
    • 制造半导体器件的方法
    • US20100075477A1
    • 2010-03-25
    • US12495240
    • 2009-06-30
    • Ji Hyun Seo
    • Ji Hyun Seo
    • H01L21/762H01L21/336
    • H01L21/76232H01L21/76213H01L27/11521
    • An embodiment of the disclosure relates to a method of manufacturing semiconductor devices. According to this embodiment, a tunnel insulating layer, a conductive layer for a floating gate, and a hard mask layer are sequentially formed over a semiconductor substrate. Isolation trenches are formed by etching the hard mask layer, the conductive layer for the floating gate, the tunnel insulating layer, and the semiconductor substrate. Isolation structures are formed by filling the isolation trenches with an insulating layer. Upper sidewalls of the isolation trenches are exposed by etching predetermined thickness of the isolation structures. Ion implantation regions are formed in the exposed upper sidewalls of the isolation trenches by performing an ion implantation process.
    • 本公开的实施例涉及制造半导体器件的方法。 根据本实施例,在半导体衬底上依次形成隧道绝缘层,浮栅用导电层和硬掩模层。 通过蚀刻硬掩模层,浮栅的导电层,隧道绝缘层和半导体衬底形成隔离沟槽。 通过用绝缘层填充隔离沟槽形成隔离结构。 通过蚀刻隔离结构的预定厚度来暴露隔离沟槽的上侧壁。 离子注入区域通过进行离子注入工艺形成在隔离沟槽的暴露的上侧壁中。