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1. 发明授权

US08980739B2 Solder collapse free bumping process of semiconductor device 有权
标题翻译：半导体器件的无塌陷焊接过程
公开(公告)号：US08980739B2
公开(公告)日：2015-03-17
申请号：US13473728
申请日：2012-05-17
申请人： Moon-gi Cho , Sang-hee Lee , Jeong-woo Park
发明人： Moon-gi Cho , Sang-hee Lee , Jeong-woo Park
IPC分类号： H01L21/44 , H01L23/00
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/03 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05166 , H01L2224/05647 , H01L2224/11462 , H01L2224/1147 , H01L2224/1181 , H01L2224/11849 , H01L2224/11902 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2924/00014 , H01L2924/01074 , H01L2924/00012 , H01L2924/01047 , H01L2924/01083 , H01L2924/01051 , H01L2924/01029 , H01L2924/01046
摘要： A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps.
摘要翻译：一种形成具有减少的焊料凹陷的半导体器件的凸块的方法。该方法包括制备其中焊盘从钝化层向外暴露的半导体衬底; 在半导体衬底上形成晶种层; 形成光致抗蚀剂图案以暴露焊盘上的种子层; 通过在由光致抗蚀剂图案曝光的区域上执行初级电镀形成柱; 通过在柱上进行二次电镀形成焊料层; 去除光致抗蚀剂图案; 通过对半导体衬底进行回流处理，形成焊料凸点，其中焊料部分地覆盖柱的表面; 以及除去形成在除了焊锡凸块之外的区域中的种子层的部分。

2. 发明授权

US08422834B2 Semiconductor integrated circuits including optoelectronic device for changing optical phase 有权
标题翻译：包括用于改变光学相位的光电器件的半导体集成电路
公开(公告)号：US08422834B2
公开(公告)日：2013-04-16
申请号：US12746167
申请日：2008-06-03
申请人： Jeong-Woo Park , Gyung-Ock Kim , Mi-Ran Park , Jong-Bum You
发明人： Jeong-Woo Park , Gyung-Ock Kim , Mi-Ran Park , Jong-Bum You
IPC分类号： G02F1/035 , G02F1/295 , G02B6/10 , G02B6/12
CPC分类号： G02F1/218 , G02F2001/212 , G02F2201/302
摘要： Provided is a semiconductor integrated circuit. The semiconductor integrated circuit includes a semiconductor pattern disposed on a substrate and including an optical waveguide part and a pair of recessed portions. The optical waveguide part has a thickness ranging from about 0.05 μm to about 0.5 μm. The recessed portions are disposed on both sides of the optical waveguide part and have a thinner thickness than the optical waveguide part. A first doped region and a second doped region are disposed in the recessed portions, respectively. The first and second doped regions are doped with a first conductive type dopant and a second conductive type dopant, respectively. An intrinsic region is formed in at least the optical waveguide part to contact the first and second doped regions.
摘要翻译：提供了一种半导体集成电路。半导体集成电路包括设置在基板上并且包括光波导部分和一对凹部的半导体图案。光波导部分的厚度范围为约0.05μm至约0.5μm。凹部设置在光波导部分的两侧，并且具有比光波导部分更薄的厚度。第一掺杂区域和第二掺杂区域分别设置在凹部中。第一和第二掺杂区域分别掺杂有第一导电型掺杂剂和第二导电型掺杂剂。在至少光波导部分中形成本征区域以接触第一和第二掺杂区域。

3. 发明申请

US20130075905A1 Semiconductor Chips and Semiconductor Packages and Methods of Fabricating the Same 审中-公开
标题翻译：半导体芯片和半导体封装及其制造方法
公开(公告)号：US20130075905A1
公开(公告)日：2013-03-28
申请号：US13602581
申请日：2012-09-04
申请人： Ju-il Choi , Jeong-Woo Park , Jeonggi Jin , Hyungseok Kim
发明人： Ju-il Choi , Jeong-Woo Park , Jeonggi Jin , Hyungseok Kim
IPC分类号： H01L23/48 , H01L23/532
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05571 , H01L2224/05599 , H01L2224/13009 , H01L2224/13023 , H01L2224/13111 , H01L2224/13147 , H01L2224/13184 , H01L2224/13562 , H01L2224/13583 , H01L2224/13644 , H01L2224/13647 , H01L2224/13664 , H01L2224/13666 , H01L2224/13669 , H01L2224/13681 , H01L2224/13686 , H01L2224/14181 , H01L2224/16146 , H01L2224/16225 , H01L2224/16237 , H01L2224/16503 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01327 , H01L2924/15788 , H01L2924/00 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/00012 , H01L2224/05552
摘要： A semiconductor device includes a substrate and a through via penetrating the substrate. The through via has a protruding portion at a first end thereof extending out from a first surface of the substrate and a second end of the via contacting an interconnection line proximate a second, opposite, end of the substrate. A wetting layer is positioned between the via and the substrate and extends over the protruding portion of the via. The wetting layer includes a material selected to improve an adhesive strength between the wetting layer and a solder ball contacting the wetting layer extending over the protruding portion of the via when a solder ball is coupled to the wetting layer.
摘要翻译：半导体器件包括基板和穿透基板的贯通孔。通孔在其第一端处具有从基板的第一表面延伸出的突出部分，并且通孔的第二端接近靠近基板的第二相对端的互连线。润湿层位于通孔和基底之间并且在通孔的突出部分上延伸。润湿层包括选择的材料，以便当焊球与润湿层耦合时，改善润湿层与接触润湿层的焊球之间的粘合强度，该润湿层在通孔的突出部分上延伸。

4. 发明授权

US08320037B2 Electro-optic device 有权
标题翻译：电光装置
公开(公告)号：US08320037B2
公开(公告)日：2012-11-27
申请号：US12652623
申请日：2010-01-05
申请人： Jeong Woo Park , Jongbum You , Gyungock Kim
发明人： Jeong Woo Park , Jongbum You , Gyungock Kim
IPC分类号： G02F1/01 , H01L31/0232
CPC分类号： G02F1/025 , G02F1/2257 , G02F2001/212
摘要： An electro-optic device is provided. The electro-optic device includes a junction layer disposed between a first conductivity type semiconductor layer and a second conductivity type semiconductor layer to which a reverse vias voltage is applied. The first conductivity type semiconductor layer and the second conductivity type semiconductor layer have an about 2 to 4-time doping concentration difference therebetween, thus making it possible to provide the electro-optic device optimized for high speed, low power consumption and high integration.
摘要翻译：提供了一种电光装置。电光器件包括设置在第一导电类型半导体层和施加反向通孔电压的第二导电类型半导体层之间的结层。第一导电型半导体层和第二导电类型半导体层之间具有约2至4倍的掺杂浓度差，因此可以提供优化用于高速度，低功耗和高集成度的电光装置。

5. 发明申请

US20120111607A1 CIRCUIT BOARD WITH HIGH-DENSITY CIRCUIT PATTERNS 有权
标题翻译：具有高密度电路图形的电路板
公开(公告)号：US20120111607A1
公开(公告)日：2012-05-10
申请号：US13354438
申请日：2012-01-20
申请人： Shuhichi OKABE , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Jeong-Woo Park , Ji-Eun Kim
发明人： Shuhichi OKABE , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Jeong-Woo Park , Ji-Eun Kim
IPC分类号： H05K1/02
CPC分类号： H05K1/0265 , H05K1/116 , H05K3/107 , H05K3/108 , H05K3/205 , H05K3/421 , H05K2201/0379 , H05K2201/0394 , H05K2201/09509 , H05K2201/09736 , H05K2203/0361
摘要： A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein.
摘要翻译：一种电路板，包括：具有沟槽的绝缘体; 形成为埋入沟槽的一部分的第一电路图案; 以及形成在其中形成有沟槽的绝缘体的表面上的第二电路图案。

6. 发明授权

US08129840B2 Semiconductor package and methods of manufacturing the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US08129840B2
公开(公告)日：2012-03-06
申请号：US12503274
申请日：2009-07-15
申请人： Chajea Jo , Uihyoung Lee , Jae-hyun Phee , Jeong-Woo Park , Ha-Young Yim
发明人： Chajea Jo , Uihyoung Lee , Jae-hyun Phee , Jeong-Woo Park , Ha-Young Yim
IPC分类号： H01L21/48
CPC分类号： H01L21/563 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L2224/0401 , H01L2224/05558 , H01L2224/06051 , H01L2224/06102 , H01L2224/1146 , H01L2224/11472 , H01L2224/11505 , H01L2224/11902 , H01L2224/11912 , H01L2224/13027 , H01L2224/13082 , H01L2224/13111 , H01L2224/13113 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13169 , H01L2224/14104 , H01L2224/1411 , H01L2224/14131 , H01L2224/17107 , H01L2224/73204 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01105 , H01L2924/014 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package include a substrate including a plurality of pads and a plurality of bumps evenly disposed on an entire region of the substrate regardless of an arrangement of the plurality of pads. According to the present invention, a simplification of a process can be accomplished, a cost of a process can be reduced, reliability can be improved and an under-filling can become easy.
摘要翻译：半导体封装以及半导体封装的制造方法。半导体封装包括基板，其包括多个焊盘和均匀地设置在基板的整个区域上的多个凸块，而与多个焊盘的布置无关。根据本发明，可以实现工艺的简化，可以降低工艺成本，可以提高可靠性，并且能够容易地进行填充不足。

7. 发明授权

US07992291B2 Method of manufacturing a circuit board 有权
标题翻译：制造电路板的方法
公开(公告)号：US07992291B2
公开(公告)日：2011-08-09
申请号：US11976070
申请日：2007-10-19
申请人： Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
发明人： Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
IPC分类号： H05K3/20 , H05K1/18
CPC分类号： H05K3/205 , H01L21/4846 , H01L23/49816 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/15311 , H05K3/4007 , H05K2201/09745 , H05K2201/10674 , H05K2203/0338 , H05K2203/0435 , Y10T29/49126 , Y10T29/49128 , Y10T29/49144 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165
摘要： A method of manufacturing a circuit board, which includes a bump pad on which a solder bump may be placed, may include forming a solder pad on a surface of a first carrier; forming a metal film, which covers the solder pad and which extends to a bump pad forming region; forming a circuit layer and a circuit pattern, which are electrically connected with the metal film, on a surface of the first carrier; pressing the first carrier and an insulator such that a surface of the first carrier and the insulator faces each other; and removing the first carrier. Utilizing this method, the amount of solder for the contacting of a flip chip can be adjusted, and solder can be filled inside the board, so that after installing a chip, the overall thickness of the package can be reduced.
摘要翻译：一种制造电路板的方法，包括可以放置焊锡凸块的凸块焊盘，可以包括在第一载体的表面上形成焊盘; 形成覆盖焊盘并延伸到凸块焊盘形成区域的金属膜; 在所述第一载体的表面上形成与所述金属膜电连接的电路层和电路图案; 按压所述第一载体和绝缘体，使得所述第一载体和所述绝缘体的表面彼此面对; 并移除第一载体。利用这种方法，可以调节用于接合倒装芯片的焊料的量，并且可以在板内填充焊料，使得在安装芯片之后，可以减小封装的整体厚度。

8. 发明申请

US20110058764A1 ELECTRO-OPTIC MODULATING DEVICE 有权
标题翻译：电光调制装置
公开(公告)号：US20110058764A1
公开(公告)日：2011-03-10
申请号：US12872881
申请日：2010-08-31
申请人： Gyungock KIM , Jeong Woo Park , Jongbum You , Sang Gi Kim , Sanghoon Kim , In Gyoo Kim , Jiho Joo , Duk Jun Kim , Dongwoo Suh , Sahnggi Park , Ki Seok Jang , Junghyung Pyo , Kap-Joong Kim , Do Won Kim , Dae Seo Park
发明人： Gyungock KIM , Jeong Woo Park , Jongbum You , Sang Gi Kim , Sanghoon Kim , In Gyoo Kim , Jiho Joo , Duk Jun Kim , Dongwoo Suh , Sahnggi Park , Ki Seok Jang , Junghyung Pyo , Kap-Joong Kim , Do Won Kim , Dae Seo Park
IPC分类号： G02F1/035
CPC分类号： G02F1/025 , G02F2201/063
摘要： Provided is an electro-optic modulating device. The electro-optic modulating device includes an optical waveguide with a vertical structure and sidewalls of the vertical structure are used to configure a junction.
摘要翻译：提供了一种电光调制装置。电光调制装置包括具有垂直结构的光波导，垂直结构的侧壁用于构造接合部。

9. 发明申请

US20100201113A1 MULTIPURPOSE COVER SUPPORTER 审中-公开
标题翻译：多用途支架
公开(公告)号：US20100201113A1
公开(公告)日：2010-08-12
申请号：US12678986
申请日：2008-09-19
申请人： Jeong Woo Park
发明人： Jeong Woo Park
IPC分类号： B42D3/00
CPC分类号： B42F13/402 , B42D3/126 , B42D3/16
摘要： A multipurpose cover supporter includes a front cover (20) and a rear cover (30) foldably connected with each other by a main connection part (10); first front and rear foldable covers (25 and 35) connected to outer surfaces of the front and rear covers (20 and 30) along first folding lines (25a and 35a) and overlapping with the front and rear covers (20 and 30); second front and rear foldable covers (26 and 36) connected to the outer surfaces of the front and rear covers (20 and 30) along second folding lines (26a and 36a) above the first front and rear foldable covers (25 and 35) and overlapping with the front and rear covers (20 and 30); first angle maintaining parts connected between the front and rear covers (20 and 30) and the first front and rear foldable covers (25 and 35) to maintain an angle defined therebetween when they are unfolded from each other; and second angle maintaining parts connected between the front and rear covers (20 and 30) and the second front and rear foldable covers (26 and 36) to maintain an angle defined therebetween when they are unfolded from each other.
摘要翻译：多功能盖支撑件包括通过主连接部分（10）彼此可折叠地连接的前盖（20）和后盖（30）。沿着第一折叠线（25a和35a）连接到前盖和后盖（20和30）的外表面并与前盖和后盖重叠的第一前后可折叠盖（25和35）; 第二前后可折叠盖（26和36），其沿着第一前后可折叠盖（25和35）上方的第二折叠线（26a和36a）连接到前盖和后盖（20和30）的外表面，以及与前后盖（20和30）重叠; 连接在前盖和后盖（20,30）之间的第一角度保持部分和第一前后可折叠盖（25和35），以在彼此展开时保持其间限定的角度; 以及连接在前盖和后盖（20,30）之间的第二角度保持部分和第二前后可折叠盖（26和36），以在它们彼此展开时保持其间限定的角度。

10. 发明授权

US07646942B2 Silicon semiconductor based high-speed ring optical modulator 失效
标题翻译：硅半导体高速环形光调制器
公开(公告)号：US07646942B2
公开(公告)日：2010-01-12
申请号：US11833004
申请日：2007-08-02
申请人： Jeong Woo Park , Gyungock Kim , Hyun Soo Kim , Bongki Mheen
发明人： Jeong Woo Park , Gyungock Kim , Hyun Soo Kim , Bongki Mheen
IPC分类号： G02F1/035 , G02B6/26
CPC分类号： G02F1/025 , G02F1/3133 , G02F2001/0152 , G02F2203/15
摘要： Provided is a high-speed ring optical modulator based on a silicon semiconductor, having increased optical modulation speed. The high-speed ring optical modulator includes a ring optical waveguide including a portion in which the refractive index varies, that is, a refractive index variation portion, and an optical waveguide having a constant refractive index. The refractive index variation portion comprises a bipolar transistor. Thus carriers can be supplied to and discharged from the refractive index variation portion, through which light is transmitted, at high speed, and thus the optical modulation speed can be increased.
摘要翻译：提供了一种基于硅半导体的高速环形光调制器，其具有增加的光调制速度。高速环形光调制器包括环形光波导，其包括折射率变化的部分，即折射率变化部分和具有恒定折射率的光波导。折射率变化部分包括双极晶体管。因此，可以高速地将载流子提供给发射光的折射率变化部分放出，从而可以提高光调制速度。

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