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    • 4. 发明申请
    • Integer transforming device for moving-picture encoder
    • 移动图像编码器的整数变换装置
    • US20060259536A1
    • 2006-11-16
    • US11397763
    • 2006-04-03
    • Eon-Pyo HongDong-Soo HarJeong-A LeeHyun-Sup Shin
    • Eon-Pyo HongDong-Soo HarJeong-A LeeHyun-Sup Shin
    • G06F7/50
    • H04N19/60
    • An integer transforming device for a moving-picture compression encoder, associated with the H.264 standard, comprising: a first adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for input data, generating data extended by a predetermined bit number; a second adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for a shifted result of output data of the first adding/subtracting stage, generating data extended by a predetermined bit number; a third adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for an operation result of the second adding/subtracting stage, generating data extended by a predetermined bit number; and a fourth adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for a shifted result of the third adding/subtracting stage, generating data extended by a predetermined bit number.
    • 一种与H.264标准相关联的用于运动图像压缩编码器的整数变换装置,包括:包括多个加法器/减法器的第一加法/减法器,用于对输入数据执行加法和减法,产生由预定位延长的数据 数; 第二加/减级包括多个加法器/减法器,用于对第一加法/减法器的输出数据的移位结果执行加法和减法,产生以预定位数扩展的数据; 第三加/减级包括多个加法器/减法器,用于对第二加/减级的运算结果执行加法和减法,产生以预定比特数扩展的数据; 以及包括多个加法器/减法器的第四加/减级,以对第三加/减级的移位结果执行加法和减法,产生由预定位数扩展的数据。
    • 8. 发明申请
    • SELF-HEALING, FAULT-TOLERANT FPGA COMPUTATION UNIT AND STRUCTURE
    • 自我维护,故障容错FPGA计算单元和结构
    • US20150082101A1
    • 2015-03-19
    • US14395755
    • 2012-06-05
    • Jeong A LeeBaig Hasan
    • Jeong A LeeBaig Hasan
    • G06F11/10G06F11/273
    • G06F11/10G06F11/2025G06F11/2038G06F11/2051H03K19/173H03K19/17764
    • The present invention relates to a computation cell and a self-healing, fault-tolerant FPGA architecture and, more particularly, to a computation cell and an FPGA including the same, which can detect a transient internal error or permanent internal error by inputting an original function and a spare function and comparing a prestored error detection code with a generated error detection code signal. The computation cell and the self-healing, fault-tolerant FPGA architecture of the present invention can reconfigure stem cells and look-up tables included in the computation cell and can output a normal output signal even if a transient error or a permanent error is generated in an computation cell such that the corresponding computation cell and an computation tile can be normally operated.
    • 本发明涉及一种计算单元和一种自修复的容错FPGA架构,更具体地说,涉及一种可以通过输入原始信号来检测瞬态内部错误或永久内部误差的计算单元和包括该单元的FPGA 功能和备用功能,并将预先存储的错误检测码与生成的错误检测码信号进行比较。 本发明的计算单元和自修复的容错FPGA架构可以重新配置包含在计算单元中的干细胞和查找表,并且即使产生瞬时错误或永久性错误也能够输出正常的输出信号 在计算单元中,使得对应的计算单元和计算瓦片可以正常工作。