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1. 发明授权

US08271820B2 Micro-processor 有权
标题翻译：微处理器
公开(公告)号：US08271820B2
公开(公告)日：2012-09-18
申请号：US12482852
申请日：2009-06-11
申请人： Ie-Ryung Park , Dong-Soo Har , Yousaf Zafar
发明人： Ie-Ryung Park , Dong-Soo Har , Yousaf Zafar
IPC分类号： G06F1/00
CPC分类号： G06F1/06 , G06F9/3869
摘要： A micro-processor includes a clock generator configured to generate a fetch clock, a decoding clock, an execution clock, and a write-back clock that are sequentially enabled; a volatile memory device configured to output pre-stored program data in response to the fetch clock; a command decoder configured to decode the program data in response to the decoding clock and generate a decoding command; an arithmetic device configured to perform an arithmetic operation according to the command of the decoding command in response to the execution clock; and a peripheral circuit device configured to be operated according to the command of the decoding command in response to the write-back clock.
摘要翻译：微处理器包括：时钟发生器，被配置为产生顺序启用的获取时钟，解码时钟，执行时钟和回写时钟; 易失性存储器装置，被配置为响应于所述获取时钟输出预存储的程序数据; 命令解码器，被配置为响应于所述解码时钟对所述节目数据进行解码并生成解码命令; 运算装置，被配置为响应于执行时钟执行根据解码命令的命令的算术运算; 以及外围电路装置，被配置为响应于所述写回时钟而根据所述解码命令的命令进行操作。

2. 发明授权

US08223860B2 OFDM system and data transmission method therefor 有权
标题翻译： OFDM系统及其数据传输方法
公开(公告)号：US08223860B2
公开(公告)日：2012-07-17
申请号：US12482859
申请日：2009-06-11
申请人： Dong-Soo Har , Eon-Pyo Hong , Jong-Yeop Lee
发明人： Dong-Soo Har , Eon-Pyo Hong , Jong-Yeop Lee
IPC分类号： H04K1/10 , H04L5/12
CPC分类号： H04L27/2614 , H04L27/2621
摘要： An OFDM system includes a frequency-time transformer configured to receive and transform input data to be transmitted to a time-domain sequence; a serial/parallel transformer configured to divide the time-domain sequence into plural sequences; a phase rotating module configured to perform phase rotation in respects to each of the divided time-domain sequences; and a minimum PAPR signal selector configured to select a sequence having a minimum peak-to-average power ratio (PAPR) among the sequences outputted from the phase rotating module.
摘要翻译： OFDM系统包括：频率 - 时间变换器，被配置为接收和变换要发送到时域序列的输入数据; 配置为将时域序列划分为多个序列的串/并联变换器; 相位旋转模块，被配置为相对于每个分割的时域序列执行相位旋转; 以及最小PAPR信号选择器，被配置为从相位旋转模块输出的序列中选择具有最小峰值与平均功率比（PAPR）的序列。

3. 发明授权

US07282946B2 Delay-insensitive data transfer circuit using current-mode multiple-valued logic 失效
标题翻译：使用电流模式多值逻辑的延迟不敏感数据传输电路
公开(公告)号：US07282946B2
公开(公告)日：2007-10-16
申请号：US11025458
申请日：2004-12-29
申请人： Dong-Soo Har , Myeong-Hoon Oh
发明人： Dong-Soo Har , Myeong-Hoon Oh
IPC分类号： H03K17/16
CPC分类号： H04L12/40013
摘要： The present invention relates to a delay-insensitive DI data transfer circuit based on a current-mode multiple-valued logic for transferring data regardless of a delay time of transmission according to a length of wire.The delay-insensitive data transfer circuit of the present invention, in a delay-insensitive data transfer circuit transferring an input request signal and a data signal from a data transmission unit to a data receiving unit, comprises: an encoder for outputting a signal which has been converted to current-level signals in response to voltage-level input of data signal and request signal from the data transmission unit; and a decoder for restoring the voltage-level signals from the current-level signals of the encoder, abstracting a data signal and a request signal from the restored voltage-level signals, and outputting the data signal and the request signal to the data receiving unit.
摘要翻译：本发明涉及一种基于用于传送数据的电流模式多值逻辑的延迟不敏感的DI数据传输电路，而不管根据电线长度的传输的延迟时间如何。本发明的延迟不敏感数据传输电路在将输入请求信号和数据信号从数据传输单元传送到数据接收单元的延迟不敏感数据传输电路中包括：编码器，用于输出具有响应于数据信号的电压电平输入和来自数据传输单元的请求信号，被转换成电流电平信号; 以及解码器，用于从编码器的当前电平信号恢复电压电平信号，从恢复的电压电平信号中抽取数据信号和请求信号，并将数据信号和请求信号输出到数据接收单元。

4. 发明授权

US07555050B2 Space-time block coding system combined with local polynomial approximation based beamformer 失效
标题翻译：空时块编码系统结合局部多项式近似波束形成器
公开(公告)号：US07555050B2
公开(公告)日：2009-06-30
申请号：US11397133
申请日：2006-04-03
申请人： Dong-Soo Har , Sun-Hee Hwang
发明人： Dong-Soo Har , Sun-Hee Hwang
IPC分类号： H04K1/10 , H04L27/28
CPC分类号： H04L1/0643 , H04L1/0631
摘要： Provided is an STBC transceiving system with LPA-based beamformer, including: an STBC encoder having branches, in number of D, to generate output signals in number of D for an input signal; a beamformer having output antennas in number of D*B, being comprised of beam-forming subarrays in number of D each having the output antennas in number of B to form a downlink beam from the D-numbered output signals of the STBC encoder; and an STBC decoder restoring an original signal by dividing a signal, which is received as one with signals transmitted through a mobile antenna from the D-numbered beam-forming subarrays, into signals in number of D in accordance with the subarrays in consideration of channel characteristics.
摘要翻译：提供了一种具有基于LPA的波束形成器的STBC收发系统，包括：具有D个分支的STBC编码器，用于产生用于输入信号的D数量的输出信号; 具有D * B数量的输出天线的波束形成器，由数量为D的输出天线的D个波束形成子阵列组成，以从STBC编码器的D编号的输出信号形成下行链路波束; 以及STBC解码器，通过将根据来自D编号的波束形成子阵列的通过移动天线发送的信号作为一个信号被分割成根据基于考虑到信道的子阵列的D数字的信号来恢复原始信号特点

5. 发明授权

US07313672B2 Intellectual property module for system-on-chip 有权
标题翻译：芯片系统的知识产权模块
公开(公告)号：US07313672B2
公开(公告)日：2007-12-25
申请号：US11048595
申请日：2005-02-01
申请人： Fahad Ali Mujahid , Dong-Soo Har
发明人： Fahad Ali Mujahid , Dong-Soo Har
IPC分类号： G06F3/00
CPC分类号： G06F15/16
摘要： Disclosed is an IP module for an SOC which brings easiness in designing system architecture and integration. The IP module of the invention includes a controller for generating a control signal for IP module with reference to a handshake signal and sending a control signal which leads the IP module to process input data in response to handshake signal; and a data processor generating output data and a modified handshake signal after processing a handshake signal and input data under the control of the controller. The present invention makes it possible to design an IP module that is easily reusable and optimized in architecture, lightening effort and time for designing and verifying an SOC by means of the proposed IP module.
摘要翻译：公开了一种用于SOC的IP模块，其容易设计系统架构和集成。本发明的IP模块包括：控制器，用于参考握手信号产生IP模块的控制信号，并发送控制信号，该控制信号使IP模块响应于握手信号来处理输入数据; 以及在控制器的控制下处理握手信号和输入数据之后，生成输出数据和修改的握手信号的数据处理器。本发明使得可以通过所提出的IP模块来设计易于可重用和优化的体系结构，减轻工作量和设计和验证SOC的IP模块。

6. 发明授权

US07519643B2 Montgomery multiplier for RSA security module 失效
标题翻译：用于RSA安全模块的蒙哥马利乘数
公开(公告)号：US07519643B2
公开(公告)日：2009-04-14
申请号：US11025408
申请日：2004-12-29
申请人： Dong-Soo Har , Dong-Wook Lee
发明人： Dong-Soo Har , Dong-Wook Lee
IPC分类号： G06F7/38 , G06F7/52
CPC分类号： G06F7/728 , G06F2207/7266
摘要： A Montgomery multiplier for providing security of information used in smart cards from hacking by a differential power analysis attack by minimizing power consumption difference by the input data. More particularly, the Montgomery multiplier applies an asynchronous dual rail lines method wherein two lines DATAFALSE and DATATRUE are used to represent one binary data such that in order to represent binary data ‘0’, a logical high signal is applied to the DATAFALSE line, and a logical low signal is applied to the DATATRUE line. Conversely, to represent binary data ‘1’, a logical low signal is applied to the DATAFALSE line, and a logical high signal is applied to the DATATRUE line. That is, when the data is represented by the asynchronous dual rail lines method, whatever the binary data value is, the same number of logical high states and logical low states are generated. As a result, whatever binary data is to be operated, the power consumption difference of the circuit is minimized.
摘要翻译：一个蒙哥马利乘数，用于通过差分功率分析攻击提供智能卡中使用的信息安全性，从而通过输入数据最小化功耗差异。更具体地说，Montgomery乘法器应用异步双轨线路方法，其中两条线DATAFALSE和DATATRUE用于表示一个二进制数据，使得为了表示二进制数据'0'，逻辑高信号被施加到DATAFALSE线，并且逻辑低信号被应用于DATATRUE线。相反，为了表示二进制数据'1'，逻辑低信号被施加到DATAFALSE行，并且逻辑高信号被施加到DATATRUE行。也就是说，当数据由异步双轨线方法表示时，无论二进制数据值如何，都产生相同数量的逻辑高状态和逻辑低状态。因此，无论二进制数据如何运行，电路的功耗差异最小化。

7. 发明授权

US07170431B2 Data transmitting circuit and method based on differential value data encoding 失效
标题翻译：基于差分值数据编码的数据传输电路及方法
公开(公告)号：US07170431B2
公开(公告)日：2007-01-30
申请号：US10967647
申请日：2004-10-14
申请人： Eun-Gu Jung , Jeong-Gun Lee , Dong-Soo Har
发明人： Eun-Gu Jung , Jeong-Gun Lee , Dong-Soo Har
IPC分类号： H03M7/00
CPC分类号： H03M7/3044 , H03M7/18
摘要： Disclosed is a data transmitting circuit and a method based on a differential value data encoding to reduce a data transmitting time by transmitting an encoded differential value. The circuit comprises an encoder for encoding and outputting a differential value between a currently transmitted data value and a previously transmitted data value, wherein the encoder inverts a phase of one output signal among 2n(namely, N)-output signals in response to n-bit input value and outputs an encoded data value; and a decoder for decoding the output value of the encoder and restoring the original data value, wherein the decoder restores the original data value by adding an output value from the encoder and the previous original data value.
摘要翻译：公开了一种数据发送电路和基于差分值数据编码的方法，以通过发送编码的差分值来减少数据发送时间。该电路包括一个编码器，用于对当前传输的数据值和先前发送的数据值之间的差分值进行编码和输出，其中编码器将两个输出信号的相位反相（即N） - 响应于n位输入值输出信号并输出编码数据值; 以及解码器，用于对编码器的输出值进行解码并恢复原始数据值，其中解码器通过将来自编码器的输出值和先前的原始数据值相加来恢复原始数据值。

8. 发明申请

US20100274996A1 MICRO-PROCESSOR 有权
标题翻译：微处理器
公开(公告)号：US20100274996A1
公开(公告)日：2010-10-28
申请号：US12482852
申请日：2009-06-11
申请人： Ie-Ryung PARK , Dong-Soo Har , Yousaf Zafar
发明人： Ie-Ryung PARK , Dong-Soo Har , Yousaf Zafar
IPC分类号： G06F1/06 , G06F9/302
CPC分类号： G06F1/06 , G06F9/3869
摘要： A micro-processor includes a clock generator configured to generate a fetch clock, a decoding clock, an execution clock, and a write-back clock that are sequentially enabled; a volatile memory device configured to output pre-stored program data in response to the fetch clock; a command decoder configured to decode the program data in response to the decoding clock and generate a decoding command; an arithmetic device configured to perform an arithmetic operation according to the command of the decoding command in response to the execution clock; and a peripheral circuit device configured to be operated according to the command of the decoding command in response to the write-back clock.
摘要翻译：微处理器包括：时钟发生器，被配置为产生顺序启用的获取时钟，解码时钟，执行时钟和回写时钟; 易失性存储器装置，被配置为响应于所述获取时钟输出预存储的程序数据; 命令解码器，被配置为响应于所述解码时钟对所述节目数据进行解码并生成解码命令; 运算装置，被配置为响应于执行时钟执行根据解码命令的命令的算术运算; 以及外围电路装置，被配置为响应于所述写回时钟而根据所述解码命令的命令进行操作。

9. 发明申请

US20100272197A1 OFDM SYSTEM AND DATA TRANSMISSION METHOD THEREFOR 有权
标题翻译： OFDM系统和数据传输方法
公开(公告)号：US20100272197A1
公开(公告)日：2010-10-28
申请号：US12482859
申请日：2009-06-11
申请人： Dong-Soo HAR , Eon-Pyo HONG , Jong-Yeop LEE
发明人： Dong-Soo HAR , Eon-Pyo HONG , Jong-Yeop LEE
IPC分类号： H04L27/28
CPC分类号： H04L27/2614 , H04L27/2621
摘要： An OFDM system includes a frequency-time transformer configured to receive and transform input data to be transmitted to a time-domain sequence; a serial/parallel transformer configured to divide the time-domain sequence into plural sequences; a phase rotating module configured to perform phase rotation in respects to each of the divided time-domain sequences; and a minimum PAPR signal selector configured to select a sequence having a minimum peak-to-average power ratio (PAPR) among the sequences outputted from the phase rotating module.
摘要翻译： OFDM系统包括：频率 - 时间变换器，被配置为接收和变换要发送到时域序列的输入数据; 配置为将时域序列划分为多个序列的串/并联变换器; 相位旋转模块，被配置为相对于每个分割的时域序列执行相位旋转; 以及最小PAPR信号选择器，被配置为从相位旋转模块输出的序列中选择具有最小峰值与平均功率比（PAPR）的序列。

10. 发明授权

US07816956B2 Power-on reset circuit 有权
标题翻译：上电复位电路
公开(公告)号：US07816956B2
公开(公告)日：2010-10-19
申请号：US12182439
申请日：2008-07-30
申请人： Dong-Soo Har , Yousaf Zafar
发明人： Dong-Soo Har , Yousaf Zafar
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G06F1/24
摘要： A power-on reset circuit according to an embodiment of the present invention includes an input control unit configured to generate a default input signal in response to a power-on reset signal and a clock, a counting unit configured to perform a counting operation in response to the default input signal to generate a count offset signal, and a power-on reset unit configured to perform a counting operation in response to the count offset signal to generate the power-on reset signal.
摘要翻译：根据本发明的实施例的上电复位电路包括：输入控制单元，被配置为响应于上电复位信号和时钟产生默认输入信号;计数单元，被配置为响应于执行计数操作到所述默认输入信号以产生计数偏移信号，以及上电复位单元，被配置为响应于所述计数偏移信号执行计数操作以产生所述上电复位信号。

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