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1. 发明授权

US07517737B2 Structures for and method of silicide formation on memory array and peripheral logic devices 有权
标题翻译：存储器阵列和外围逻辑器件上硅化物形成的结构和方法
公开(公告)号：US07517737B2
公开(公告)日：2009-04-14
申请号：US11672150
申请日：2007-02-07
申请人： Yi Hung Li , Jen Chuan Pan , Jongoh Kim
发明人： Yi Hung Li , Jen Chuan Pan , Jongoh Kim
IPC分类号： H01L21/335
CPC分类号： H01L29/66833 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness. Dopants are implanted for formation of source and drain regions in the second and third areas. A silicon nitride spacer material is deposited over the word lines and gates, and etched to form sidewall spacers on the gates. Dopants are implanted aligned with the sidewall spacers in the second and third areas. The gate dielectric layers are selectively etched to expose the substrate adjacent the sidewall spacers, and to expose word lines and gates without exposing the substrate in the bit line contract regions. A self-aligned silicide formation is then applied. A portion of the charge trapping structure in the bit line contact regions acts as a mask to prevent silicide formation. An interlayer dielectric and bit line contacts are formed in the bit line contact regions. Patterned conductor layers are formed over the interlayer dielectric.
摘要翻译：通过包括在第一区域上形成具有第一厚度的电荷捕获结构的方法来描述衬底上的存储器件和外围电路。为低压晶体管形成具有第二厚度的第一栅介质层。形成具有大于第二厚度的第三厚度的第二栅极介电层，用于高压晶体管。沉积并图案化多晶硅以限定字线和晶体管栅极。第二栅极电介质层的厚度在与栅极相邻的区域以及源极和漏极区域上的厚度减小到接近第二厚度的厚度。植入掺杂剂以在第二和第三区域中形成源区和漏区。氮化硅间隔物材料沉积在字线和栅极上，并被蚀刻以在栅极上形成侧壁间隔物。在第二和第三区域中注入与侧壁间隔物对准的掺杂剂。选择性地蚀刻栅极电介质层以暴露邻近侧壁间隔物的衬底，并暴露字线和栅极，而不会在位线收缩区域中暴露衬底。然后施加自对准的硅化物形成。位线接触区域中的电荷俘获结构的一部分用作掩模以防止形成硅化物。在位线接触区域中形成层间电介质和位线接触。图案化的导体层形成在层间电介质上。

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