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1. 发明授权

US09092622B2 Random timeslot controller for enabling built-in self test module 有权
标题翻译：随机时隙控制器，用于启用内置自检模块
公开(公告)号：US09092622B2
公开(公告)日：2015-07-28
申请号：US13589580
申请日：2012-08-20
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F21/55
CPC分类号： G06F21/558 , G06F21/556 , G06F21/755
摘要： A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.
摘要翻译：一种具有第一处理器，第二处理器，第二处理器的本地存储器和第二处理器的内置自检（BIST）控制器的数据处理系统，其可以被随机地启用以对本地存储器执行存储器访问的第二处理器，并且包括随机值发生器。该系统可以执行包括由第一处理器执行安全代码序列并且由第二处理器的BIST控制器响应于随机值生成器对第二处理器的本地存储器进行BIST存储器访问的方法。执行BIST存储器访问同时执行安全代码序列。

2. 发明授权

US08674406B2 Extended wavelength digital alloy NBN detector 有权
标题翻译：扩展波长数字合金NBN检测器
公开(公告)号：US08674406B2
公开(公告)日：2014-03-18
申请号：US12837444
申请日：2010-07-15
申请人： Jeffrey W. Scott , George Paloczi
发明人： Jeffrey W. Scott , George Paloczi
IPC分类号： H01L31/00
CPC分类号： H01L31/035236 , B82Y20/00 , H01L27/142 , H01L27/14649 , H01L31/0232 , H01L31/0304 , H01L31/03046 , H01L31/1035 , H01L31/184 , H01L31/1844 , H01L33/14 , H01L33/30 , Y02E10/544
摘要： A strain-balanced photodetector is provided for detecting infrared light at an extended cutoff wavelength in the range of 4.5 μm or more. An InAsSb absorber layer has an Sb content is grown in a lattice-mismatched condition to a GaSb substrate, and a plurality of GaAs strain-compensating layers are interspersed within the absorber layer to balance the strain of the absorber layer due to the lattice mismatch. The strain-compensation layers allow the absorber to achieve a thickness exhibiting sufficient absorption efficiency while extending the cutoff wavelength beyond that possible in a lattice-matched state. Additionally, the strain-compensation layers are sufficiently thin to be substantially quantum-mechanically transparent such that they do not substantially affect the transmission efficiency of the absorber. The photodetector is preferably formed as a majority carrier filter photodetector exhibiting minimal dark current, and may be provided individually or in a focal plane array.
摘要翻译：提供一种应变平衡光电检测器，用于检测在4.5μm或更大的范围内的延长的截止波长的红外光。具有Sb含量的InAsSb吸收层在GaSb衬底中以格子失配的条件生长，并且多个GaAs应变补偿层散布在吸收层内，以平衡由于晶格失配引起的吸收层的应变。应变补偿层允许吸收体实现具有足够吸收效率的厚度，同时将截止波长延伸超过晶格匹配状态可能的截止波长。此外，应变补偿层足够薄以使其基本上是量子力学上透明的，使得它们基本上不影响吸收体的传输效率。优选地，光电检测器形成为显示最小暗电流的多数载波滤波器光电检测器，并且可以单独地或在焦平面阵列中提供。

3. 发明申请

US20140068349A1 DATA PROCESSOR DEVICE FOR HANDLING A WATCHPOINT AND METHOD THEREOF 有权
标题翻译：用于处理观察点的数据处理器装置及其方法
公开(公告)号：US20140068349A1
公开(公告)日：2014-03-06
申请号：US13827004
申请日：2013-03-14
申请人： JEFFREY W. SCOTT , William C. Moyer
发明人： JEFFREY W. SCOTT , William C. Moyer
IPC分类号： G06F11/34
CPC分类号： G06F11/3495 , G06F11/3636 , G06F11/3656
摘要： During a debug mode of operation of a data processor, it is determined at the data processor that a watchpoint event has occurred, and in response, an operating condition of a trace FIFO that stores trace information not yet communicated to a debugger is changed. For example, the occurrence of a FIFO flush watchpoint results in trace information being selectively flushed from the trace FIFO based on a state of the FIFO before the trace information has been communicated to a trace analyzer.
摘要翻译：在数据处理器的调试操作模式期间，在数据处理器确定观察点事件已经发生，并且作为响应，存储跟尚未传送到调试器的跟踪信息的跟踪FIFO的操作条件被改变。例如，FIFO跟踪观察点的发生导致在跟踪信息已被传送到跟踪分析器之前，基于FIFO的状态，从跟踪FIFO中选择性地刷新跟踪信息。

4. 发明授权

US08362520B2 Sub-pixel nBn detector 有权
公开(公告)号：US08362520B2
公开(公告)日：2013-01-29
申请号：US13151085
申请日：2011-06-01
申请人： Jeffrey W. Scott , Colin E. Jones , Ernie J. Caine , Charles A. Cockrum
发明人： Jeffrey W. Scott , Colin E. Jones , Ernie J. Caine , Charles A. Cockrum
IPC分类号： H01L31/102
CPC分类号： H01L31/035281 , H01L27/146 , H01L27/14601 , H01L27/14603 , H01L27/14638 , H01L27/14643 , H01L27/14694 , H01L31/0304 , H01L31/101 , H01L31/102 , Y02E10/50
摘要： A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.

5. 发明申请

US20120331309A1 USING BUILT-IN SELF TEST FOR PREVENTING SIDE CHANNEL SECURITY ATTACKS ON MULTI-PROCESSOR SYSTEMS 有权
标题翻译：使用内置自检来防止多处理器系统的侧面通道安全攻击
公开(公告)号：US20120331309A1
公开(公告)日：2012-12-27
申请号：US13169664
申请日：2011-06-27
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F21/00
CPC分类号： G06F21/755
摘要： A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which performs BIST memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.
摘要翻译：一种具有第一处理器，第二处理器，第二处理器的本地存储器和第二处理器的内置自检（BIST）控制器的数据处理系统，其对第二处理器的本地存储器执行BIST存储器访问并且包括随机值生成器。该系统可以执行包括由第一处理器执行安全代码序列并且由第二处理器的BIST控制器响应于随机值生成器对第二处理器的本地存储器进行BIST存储器访问的方法。执行BIST存储器访问同时执行安全代码序列。

6. 发明授权

US08205068B2 Branch target buffer allocation 有权
标题翻译：分支目标缓冲区分配
公开(公告)号：US08205068B2
公开(公告)日：2012-06-19
申请号：US12181363
申请日：2008-07-29
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A data processing system and method are provided for allocating an entry in a branch target buffer (BTB). The method comprises: receiving a branch instruction to be executed in a data processor; determining that the BTB does not include an entry corresponding to the branch instruction; identifying an entry in the BTB for allocation, the identified entry in the BTB comprising a target identifier and a first prediction value for a previously received branch instruction; determining whether to allocate the branch instruction to the identified entry in the BTB based on a comparison of the first prediction value to a second prediction value, wherein the second prediction value is generated from a branch history table (BHT); and allocating the branch instruction to the identified entry if the second prediction value indicates a more strongly taken prediction than the first prediction value.
摘要翻译：提供了一种用于在分支目标缓冲器（BTB）中分配条目的数据处理系统和方法。该方法包括：接收要在数据处理器中执行的分支指令; 确定BTB不包括对应于分支指令的条目; 识别BTB中用于分配的条目，BTB中识别的条目包括目标标识符和用于先前接收到的分支指令的第一预测值; 基于第一预测值与第二预测值的比较，确定是否将分支指令分配给BTB中的识别条目，其中从分支历史表（BHT）生成第二预测值; 以及如果所述第二预测值指示比所述第一预测值更强烈地采取的预测，则将所述分支指令分配给所识别的条目。

7. 发明授权

US08042002B2 Method and apparatus for handling shared hardware and software debug resource events in a data processing system 有权
标题翻译：用于在数据处理系统中处理共享硬件和软件调试资源事件的方法和装置
公开(公告)号：US08042002B2
公开(公告)日：2011-10-18
申请号：US12016664
申请日：2008-01-18
申请人： William C. Moyer , Jimmy Gumulja , Jeffrey W. Scott
发明人： William C. Moyer , Jimmy Gumulja , Jeffrey W. Scott
IPC分类号： G06F11/00
CPC分类号： G06F11/3656
摘要： For some data processing systems, it is important to be able to handle overlapping debug events generated by a shared set of debug resources which are trying to cause both exception processing and debug mode entry. However, exception processing and debug mode entry generally have conflicting requirements. In one embodiment, exception priority processing is initially given to the software debug event. Normal state saving is performed and the first instruction of the debug exception handler is fetched, but not executed. Priority is then switched from the software debug event to the hardware debug event and a debug halted state is entered. Once processing of the hardware debug event has been completed, priority is returned to the software debug event and the debug exception handler is executed.
摘要翻译：对于一些数据处理系统，重要的是能够处理由共同的一组调试资源生成的重叠调试事件，这些调试资源试图引起异常处理和调试模式的输入。但是，异常处理和调试模式条目通常具有冲突的要求。在一个实施例中，最初给出软件调试事件的异常优先级处理。执行正常状态保存，并且提取调试异常处理程序的第一条指令，但不执行。优先级然后从软件调试事件切换到硬件调试事件，并且进入调试停止状态。一旦硬件调试事件的处理完成，优先级将返回到软件调试事件，并执行调试异常处理程序。

8. 发明申请

US20110230158A1 Partitioned radio-frequency apparatus and associated methods 有权
公开(公告)号：US20110230158A1
公开(公告)日：2011-09-22
申请号：US13104822
申请日：2011-05-10
申请人： Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu Shankar Srinivasan
发明人： Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu Shankar Srinivasan
IPC分类号： H04B1/16
CPC分类号： H04B1/109 , H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064 , H04L27/2649
摘要： Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.

9. 发明授权

US07873819B2 Branch target buffer addressing in a data processor 有权
标题翻译：在数据处理器中分支目标缓冲区寻址
公开(公告)号：US07873819B2
公开(公告)日：2011-01-18
申请号：US11969116
申请日：2008-01-03
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/40 , G06F9/44
CPC分类号： G06F9/3806
摘要： A branch target buffer (BTB) receives, from a processor, a current fetch group address which corresponds to a current fetch group including a plurality of instructions. In response to the current fetch group address resulting in a group hit in the BTB, the BTB provides to the processor a branch target address corresponding to a branch instruction within the current fetch group which is indicated by a control field as valid and predicted taken. The BTB generates the branch target address using an unshared lower order target portion, corresponding to the branch instruction and located within the entry of the BTB which caused the group hit, and one of a shared higher order target portion located within the entry of the BTB which caused the group hit or a higher order portion of the current fetch group address based on a value of the control field.
摘要翻译：分支目标缓冲器（BTB）从处理器接收与包括多个指令的当前提取组对应的当前提取组地址。响应于当前提取组地址导致BTB中的组命中，BTB向处理器提供与由当前获取组中的分支指令相对应的转移目标地址，该控制字段由控制字段指示为有效和预测的。 BTB使用对应于分支指令的非共享低阶目标部分生成分支目标地址，并且位于BTB的导致该组命中的条目内，并且位于BTB的条目内的共享高阶目标部分之一这导致基于控制字段的值的组命中或当前获取组地址的较高阶部分。

10. 发明申请

US20090177875A1 BRANCH TARGET BUFFER ADDRESSING IN A DATA PROCESSOR 有权
标题翻译：分支目标缓存器在数据处理器中寻址
公开(公告)号：US20090177875A1
公开(公告)日：2009-07-09
申请号：US11969116
申请日：2008-01-03
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3806
摘要： A branch target buffer (BTB) receives, from a processor, a current fetch group address which corresponds to a current fetch group including a plurality of instructions. In response to the current fetch group address resulting in a group hit in the BTB, the BTB provides to the processor a branch target address corresponding to a branch instruction within the current fetch group which is indicated by a control field as valid and predicted taken. The BTB generates the branch target address using an unshared lower order target portion, corresponding to the branch instruction and located within the entry of the BTB which caused the group hit, and one of a shared higher order target portion located within the entry of the BTB which caused the group hit or a higher order portion of the current fetch group address based on a value of the control field.
摘要翻译：分支目标缓冲器（BTB）从处理器接收与包括多个指令的当前提取组对应的当前提取组地址。响应于当前提取组地址导致BTB中的组命中，BTB向处理器提供与由当前获取组中的分支指令相对应的转移目标地址，该控制字段由控制字段指示为有效和预测的。 BTB使用对应于分支指令的非共享低阶目标部分生成分支目标地址，并且位于BTB的导致该组命中的条目内，并且位于BTB的条目内的共享高阶目标部分之一这导致基于控制字段的值的组命中或当前获取组地址的较高阶部分。

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