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1. 发明申请

US20150370568A1 INTEGRATED CIRCUIT PROCESSOR AND METHOD OF OPERATING A INTEGRATED CIRCUIT PROCESSOR 审中-公开
标题翻译：集成电路处理器和集成电路处理器的操作方法
公开(公告)号：US20150370568A1
公开(公告)日：2015-12-24
申请号：US14655122
申请日：2013-01-10
申请人： Alistair ROBERSTON , Jeffrey W. SCOTT
发明人： ALISTAIR ROBERTSON , JEFFREY W. SCOTTT
IPC分类号： G06F9/30 , G06F9/38
摘要： A processor includes an instruction pipeline. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. In the multi-thread mode, the instruction pipeline processes multiple threads in an interleaved or simultaneous manner. In the single-thread mode, the pipeline processes a single thread. The instruction pipeline comprises multiple functional units, each of which is reserved for one thread among the multiple threads when the pipeline is in the multi-thread mode and reserved for one context layer among multiple context layers when the instruction pipeline is in the single-thread mode. A method of operating a processor is also disclosed.
摘要翻译：处理器包括指令流水线。管道可以以多线程模式和单线程模式交替运行。在多线程模式中，指令流水线以交错或同时的方式处理多个线程。在单线程模式下，流水线处理单线程。指令流水线包括多个功能单元，当管线处于多线程模式中时，多个功能单元被保留用于多个线程中的一个线程，并且当指令流水线处于单线程时被保留用于多个上下文层中的一个上下文层模式。还公开了一种操作处理器的方法。

2. 发明申请

US20120204012A1 CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM 有权
标题翻译：基于数据处理系统中的错误检测模式的可配置管道
公开(公告)号：US20120204012A1
公开(公告)日：2012-08-09
申请号：US13446930
申请日：2012-04-13
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/30 , G06F9/302 , G06F9/305 , G06F9/312
CPC分类号： G06F9/3875 , G06F9/3004 , G06F9/30181 , G06F9/30189 , G06F9/38 , G06F9/3861 , G06F9/3867 , G06F11/1004 , G06F11/1008 , G06F11/1076
摘要： A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.
摘要翻译：一种方法包括提供具有指令流水线的数据处理器，其中指令流水线具有多个指令流水线级，并且其中多条指令流水线级包括第一指令流水线级和第二指令流水线级。该方法还包括提供数据处理器指令，使数据处理器在数据处理器指令的执行期间执行第一组计算操作，如果数据处理器指令正在执行，则在第一指令流水线阶段执行第一组计算操作执行并且已经选择了第一模式，并且如果正在执行数据处理器指令并且已经选择了第二模式，则在第二指令流水线级中执行第一组计算操作。

3. 发明授权

US08224259B2 Digital architecture for radio-frequency apparatus and associated methods 有权
标题翻译：射频设备数字架构及相关方法
公开(公告)号：US08224259B2
公开(公告)日：2012-07-17
申请号：US12715361
申请日：2010-03-01
申请人： Richard T. Behrens , Tod Paulus , Mark S. Spurbeck , Vishnu S. Srinivasan , Donald A. Kerth , Jeffrey W. Scott , G. Tyson Tuttle , G. Diwakar Vishakhadatta
发明人： Richard T. Behrens , Tod Paulus , Mark S. Spurbeck , Vishnu S. Srinivasan , Donald A. Kerth , Jeffrey W. Scott , G. Tyson Tuttle , G. Diwakar Vishakhadatta
IPC分类号： H04B1/38 , H04W24/00
CPC分类号： H04B1/28 , H04B1/0003 , H04B1/38 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.
摘要翻译：射频（RF）接收机包括接收机模拟电路和接收机数字电路。接收器模拟电路驻留在第一集成电路内，并且接收器数字电路位于第二集成电路内。第二集成电路通过一位数字接口耦合到第一集成电路。接收机模拟电路接收RF信号并处理所接收的RF信号以产生数字信号。接收机模拟电路将数字信号提供给接收机数字电路。接收机数字电路包括数字下变频器电路，其将数字信号与中频（IF）本地振荡器（LO）信号混合以产生数字下变频信号。接收机数字电路还包括数字滤波器电路，其对数字下变频信号进行滤波以产生经滤波的数字信号。

4. 发明申请

US20120001288A1 SUB-PIXEL NBN DETECTOR 有权
标题翻译：子像素NBN检测器
公开(公告)号：US20120001288A1
公开(公告)日：2012-01-05
申请号：US13151085
申请日：2011-06-01
申请人： Jeffrey W. Scott , Colin E. Jones , Ernie J. Caine , Charles A. Cockrum
发明人： Jeffrey W. Scott , Colin E. Jones , Ernie J. Caine , Charles A. Cockrum
IPC分类号： H01L31/0232 , H01L31/0224
CPC分类号： H01L31/035281 , H01L27/146 , H01L27/14601 , H01L27/14603 , H01L27/14638 , H01L27/14643 , H01L27/14694 , H01L31/0304 , H01L31/101 , H01L31/102 , Y02E10/50
摘要： A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.
摘要翻译：制造二维检测器阵列（和这种阵列）的方法包括形成n掺杂的半导体光吸收层的多行和多列单独的检测器中的每一个，形成阻挡层，该阻挡层包括 AlSb，AlAsSb，AlGaAsSb，AlPSb，AlGaPSb和HgZnTe中的一种或多种，并且形成n掺杂的半导体接触区域。

5. 发明授权

US08044435B2 Sub-pixel nBn detector 有权
标题翻译：子像素nBn检测器
公开(公告)号：US08044435B2
公开(公告)日：2011-10-25
申请号：US11939464
申请日：2007-11-13
申请人： Jeffrey W. Scott , Colin E. Jones , Ernie J. Caine , Charles A. Cockrum
发明人： Jeffrey W. Scott , Colin E. Jones , Ernie J. Caine , Charles A. Cockrum
IPC分类号： H01L21/02
CPC分类号： H01L31/035281 , H01L27/146 , H01L27/14601 , H01L27/14603 , H01L27/14638 , H01L27/14643 , H01L27/14694 , H01L31/0304 , H01L31/101 , H01L31/102 , Y02E10/50
摘要： A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.
摘要翻译：制造二维检测器阵列（和这种阵列）的方法包括形成n掺杂的半导体光吸收层的多行和多列单独的检测器中的每一个，形成阻挡层，该阻挡层包括 AlSb，AlAsSb，AlGaAsSb，AlPSb，AlGaPSb和HgZnTe中的一种或多种，并且形成n掺杂的半导体接触区域。

6. 发明授权

US07937573B2 Metric for selective branch target buffer (BTB) allocation 有权
标题翻译：用于选择性分支目标缓冲区（BTB）分配的度量标准
公开(公告)号：US07937573B2
公开(公告)日：2011-05-03
申请号：US12040210
申请日：2008-02-29
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/32 , G06F9/34
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3804 , G06F9/382
摘要： A method and data processing system allocates entries in a branch target buffer (BTB). Instructions are fetched from a plurality of instructions and one of the plurality of instructions is determined to be a branch instruction. A corresponding branch target address is determined. A determination is made whether the branch target address is stored in a branch target buffer (BTB). When the branch target address is not stored in the branch target buffer, an entry in the branch target buffer is identified for allocation to receive the branch target address based upon stored metrics such as data processing cycle saving information and branch prediction state. In one form the stored metrics are stored in predetermined fields of the entries of the BTB.
摘要翻译：方法和数据处理系统在分支目标缓冲器（BTB）中分配条目。指令从多个指令中取出，并且多个指令中的一个被确定为分支指令。确定相应的分支目标地址。确定分支目标地址是否存储在分支目标缓冲器（BTB）中。当分支目标地址未被存储在分支目标缓冲器中时，识别分支目标缓冲器中的条目用于分配以基于存储的诸如数据处理周期保存信息和分支预测状态的指标来接收分支目标地址。在一种形式中，存储的度量被存储在BTB的条目的预定字段中。

7. 发明授权

US07895422B2 Selective postponement of branch target buffer (BTB) allocation 有权
标题翻译：分支目标缓冲区（BTB）分配的选择性推迟
公开(公告)号：US07895422B2
公开(公告)日：2011-02-22
申请号：US12040204
申请日：2008-02-29
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/38 , G06F9/44
CPC分类号： G06F9/3806 , G06F9/3802 , G06F9/3814 , G06F9/3844
摘要： A system and method provides branch target buffer (BTB) allocation. When a branch instruction is received, a branch target address that corresponds to the branch instruction is determined. A determination is made whether the branch target address is presently stored in a branch target buffer (BTB). When the branch target address is not presently stored in the branch target buffer, an entry in the branch target buffer is identified to receive the branch target address. A value in a field within the identified entry in the branch target buffer, such as a postponement flag (PF), is used to selectively override a replacement decision defined by predetermined branch target buffer allocation criteria. In one form, if a branch is taken, the identified entry is replaced with the branch target address in response to determining that the value in the field within the identified entry has a predetermined value.
摘要翻译：系统和方法提供分支目标缓冲区（BTB）分配。当接收到分支指令时，确定与分支指令对应的分支目标地址。确定分支目标地址是否当前存储在分支目标缓冲器（BTB）中。当分支目标地址当前不存储在分支目标缓冲器中时，识别分支目标缓冲器中的条目以接收分支目标地址。使用分支目标缓冲器中的所识别的条目中的字段中的值（诸如推迟标志（PF））来选择性地覆盖由预定分支目标缓冲器分配标准定义的替换决策。在一种形式中，如果采取分支，则响应于确定所识别的条目中的字段中的值具有预定值，将所标识的条目替换为分支目标地址。

8. 发明授权

US07515672B2 Digital access arrangement circuitry and method for connecting to phone lines having a DC holding circuit with programmable current limiting 失效
标题翻译：用于连接到具有可编程限流的DC保持电路的电话线路的数字接入配置电路和方法
公开(公告)号：US07515672B2
公开(公告)日：2009-04-07
申请号：US10679013
申请日：2003-10-03
申请人： Timothy J. Dupuis , George Tyson Tuttle , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Timothy J. Dupuis , George Tyson Tuttle , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H04L23/00
CPC分类号： H04L25/06 , H04L7/033 , H04L25/0266 , H04M11/06 , H04M19/001
摘要： A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable circuit for the DC termination for a variety of international phone standards. The invention may also be utilized with circuitry for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.
摘要翻译：可以使用数字直接访问布置（DAA）电路来终止在用户端的电话连接，其提供用于到达和来自电话线的信号的通信路径。简要描述，DAA为各种国际电话标准的DC终端提供可编程电路。本发明还可以用于跨电容隔离屏障发送和接收信号的电路。更具体地，提供了一种DC可编程直流限流模式可用的直流保持电路。在限流模式下，功率可能会在DAA集成电路外部的器件中耗散。此外，大部分功率可能会在外部无源器件（如电阻）中消散。

9. 发明授权

US07362841B2 Digital access arrangement circuitry and method for connecting to phone lines having a DC holding circuit with switchable DC termination impedance 失效
标题翻译：用于连接到具有可切换DC终端阻抗的DC保持电路的电话线路的数字接入布置电路和方法
公开(公告)号：US07362841B2
公开(公告)日：2008-04-22
申请号：US10292290
申请日：2002-11-12
申请人： Timothy J. Dupuis , George Tyson Tuttle , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Timothy J. Dupuis , George Tyson Tuttle , Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H04L23/00
CPC分类号： H04L25/06 , H04L7/033 , H04L25/0266 , H04M11/06 , H04M19/001
摘要： A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.
摘要翻译：可以使用数字直接访问布置（DAA）电路来终止在用户端的电话连接，其提供用于到达和来自电话线的信号的通信路径。简要描述，DAA提供用于各种国际电话标准的DC终端的可编程装置。本发明还可以用于在电容隔离屏障上传输和接收信号的装置。更具体地，提供了一种DC可编程直流限流模式可用的直流保持电路。在限流模式下，功率可能会在DAA集成电路外部的器件中耗散。此外，大部分功率可能会在外部无源器件（如电阻）中消散。

10. 发明授权

US07242912B2 Partitioning of radio-frequency apparatus 有权
标题翻译：射频设备分区
公开(公告)号：US07242912B2
公开(公告)日：2007-07-10
申请号：US10631166
申请日：2003-07-31
申请人： James Maligeorgos , Augusto M. Marques , Lysander Lim , G. Tyson Tuttle , Aslamali A. Rafi , Tod Paulus , Gregory T. Uehara , Jeffrey W. Scott , Richard T. Behrens , Donald A. Kerth , G. Diwakar Vishakhadatta , Vishnu S. Srinivasan , Caiyi Wang
发明人： James Maligeorgos , Augusto M. Marques , Lysander Lim , G. Tyson Tuttle , Aslamali A. Rafi , Tod Paulus , Gregory T. Uehara , Jeffrey W. Scott , Richard T. Behrens , Donald A. Kerth , G. Diwakar Vishakhadatta , Vishnu S. Srinivasan , Caiyi Wang
IPC分类号： H04B1/40
CPC分类号： H04B1/0003 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/099 , H03L7/187 , H03L7/199 , H03L7/23 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry. Automatic frequency control (AFC) circuitry may be integrated with other components of RF circuitry and may generate frequency control signals for the frequency modification circuitry based on, for example, a signal received from a temperature sensor. Digital-to-analog converter (DAC) circuitry may be integrated with other components of RF circuitry to enable all-digital frequency control communications from baseband processor circuitry to RF circuitry.
摘要翻译：包括生成具有可变频率的参考信号的晶体振荡器电路的收发器电路和频率修改电路的射频（RF）设备的组件可以以各种方式被划分，例如作为一个或多个单独的集成电路。频率修改电路可以被实现为包括数字控制的晶体振荡器（“DCXO”）电路和晶体的晶体振荡器电路的一部分。频率修改电路可以包括至少一个可变电容器件，并且可以用于产生具有可调频率的参考信号。可调参考信号可以被提供给RF装置的其他部件，和/或RF装置可以被配置为向基带处理器电路提供可调参考信号。自动频率控制（AFC）电路可以与RF电路的其它组件集成，并且可以基于例如从温度传感器接收的信号来生成用于频率修改电路的频率控制信号。数模转换器（DAC）电路可以与RF电路的其他部件集成，以实现从基带处理器电路到RF电路的全数字频率控制通信。

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