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1. 发明授权

US09236292B2 Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) 有权
标题翻译：通过原子层沉积（ALD）和化学气相沉积（CVD）选择性地沉积金属膜
公开(公告)号：US09236292B2
公开(公告)日：2016-01-12
申请号：US14133262
申请日：2013-12-18
申请人： Patricio E. Romero , Scott B. Clendenning , Jeanette M. Roberts , Florian Gstrein
发明人： Patricio E. Romero , Scott B. Clendenning , Jeanette M. Roberts , Florian Gstrein
IPC分类号： H01L21/768
CPC分类号： H01L21/76897 , C23C16/04 , C23C16/18 , C23C16/45525 , H01L21/28506 , H01L21/28562 , H01L21/76801 , H01L21/76816 , H01L21/76838 , H01L21/76849 , H01L21/76879
摘要： Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.
摘要翻译：描述了通过原子层沉积（ALD）和化学气相沉积（CVD）来选择性地沉积金属膜。在一个示例中，制造用于集成电路的金属化结构的方法包括在衬底上形成暴露表面，暴露的表面包括暴露的介电材料的区域和暴露的金属的区域。该方法还涉及使用选择性金属沉积工艺在暴露的金属的区域上形成金属层，而不在暴露的电介质材料的区域上形成金属层。

2. 发明申请

US20170148739A1 SELECTIVE DIFFUSION BARRIER BETWEEN METALS OF AN INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：US20170148739A1
公开(公告)日：2017-05-25
申请号：US15129140
申请日：2014-06-16
申请人： Jeanette M. ROBERTS , Patricio E. ROMERO , Scott B. CLENDENNING , Christopher J. JEZEWSKI , Ramanan V. CHEBIAM
发明人： Jeanette M. ROBERTS , Patricio E. ROMERO , Scott B. CLENDENNING , Christopher J. JEZEWSKI , Ramanan V. CHEBIAM
IPC分类号： H01L23/532 , H01L21/285 , H01L21/768 , H01L21/3215 , H01L23/528 , H01L23/522
CPC分类号： H01L23/53238 , H01L21/28556 , H01L21/28562 , H01L21/28568 , H01L21/288 , H01L21/3215 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L21/76855 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L24/17 , H01L25/105 , H01L2224/16225 , H01L2924/0002 , H01L2924/15311 , H05K1/181 , H05K2201/10734
摘要： Embodiments of the present disclosure describe a selective diffusion barrier between metals of an integrated circuit (IC) device and associated techniques and configurations. In one embodiment, an apparatus includes a dielectric material, a first interconnect structure comprising a first metal disposed in the dielectric material, a second interconnect structure comprising a second metal disposed in the dielectric material and electrically coupled with the first interconnect structure and a diffusion barrier disposed at an interface between the first interconnect structure and the second interconnect structure, wherein the first metal and the second metal have a different chemical composition, material of the diffusion barrier and the second metal have a different chemical composition and material of the diffusion barrier is not disposed directly between the second metal and the dielectric material. Other embodiments may be described and/or claimed.

3. 发明申请

US20150170961A1 SELECTIVE AREA DEPOSITION OF METAL FILMS BY ATOMIC LAYER DEPOSITION (ALD) AND CHEMICAL VAPOR DEPOSITION (CVD) 有权
标题翻译：通过原子层沉积（ALD）和化学气相沉积（CVD）的金属膜选择区沉积
公开(公告)号：US20150170961A1
公开(公告)日：2015-06-18
申请号：US14133262
申请日：2013-12-18
申请人： Patricio E. Romero , Scott B. Clendenning , Jeanette M. Roberts , Florian Gstrein
发明人： Patricio E. Romero , Scott B. Clendenning , Jeanette M. Roberts , Florian Gstrein
IPC分类号： H01L21/768
CPC分类号： H01L21/76897 , C23C16/04 , C23C16/18 , C23C16/45525 , H01L21/28506 , H01L21/28562 , H01L21/76801 , H01L21/76816 , H01L21/76838 , H01L21/76849 , H01L21/76879
摘要： Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.
摘要翻译：描述了通过原子层沉积（ALD）和化学气相沉积（CVD）来选择性地沉积金属膜。在一个示例中，制造用于集成电路的金属化结构的方法包括在衬底上形成暴露表面，暴露的表面包括暴露的介电材料的区域和暴露的金属的区域。该方法还涉及使用选择性金属沉积工艺在暴露的金属的区域上形成金属层，而不在暴露的电介质材料的区域上形成金属层。

4. 发明申请

US20080076058A1 Luminescent photoresist 审中-公开
标题翻译：发光光刻胶
公开(公告)号：US20080076058A1
公开(公告)日：2008-03-27
申请号：US11502916
申请日：2006-08-11
申请人： Michael J. Leeson , Heidi B. Cao , Wang Yueh , Jeanette M. Roberts
发明人： Michael J. Leeson , Heidi B. Cao , Wang Yueh , Jeanette M. Roberts
IPC分类号： G03F7/004
CPC分类号： G03F7/0045 , G03F7/2022 , G03F7/38
摘要： A photoresist composition (phosphoresist) including a resist capable of activation when exposed to electromagnetic energy within a first bandwidth, but relatively insensitive to electromagnetic energy within a second bandwidth and a third bandwidth, and also including a phosphor material included in the photoresist and capable of activation when exposed to electromagnetic energy within the second bandwidth. Photo-luminescent centers included in the phosphoresist are associated with the phosphor material and are capable of emitting luminescence within the first bandwidth in response to exposure to electromagnetic energy within the third bandwidth. The phosphoresist may be disposed as a relatively thin and uniform layer at a surface of a substrate, such as a semiconductor substrate.
摘要翻译：一种光致抗蚀剂组合物（磷光阻剂），其包括当在第一带宽内暴露于电磁能量时能够激活但在第二带宽和第三带宽内对电磁能量相对不敏感的抗蚀剂，并且还包括包含在光致抗蚀剂中的磷光体材料，在第二个带宽内暴露于电磁能时激活。包含在磷光抗蚀剂中的光致发光中心与磷光体材料相关联并且能够响应于在第三带宽内的电磁能量的暴露而在第一带宽内发射发光。磷光阻剂可以在诸如半导体衬底的衬底的表面处设置为相对薄且均匀的层。

5. 发明授权

US07226718B2 Non-outgassing low activation energy resist 失效
标题翻译：非除气低活化能抵抗
公开(公告)号：US07226718B2
公开(公告)日：2007-06-05
申请号：US11228589
申请日：2005-09-15
申请人： Heidi B. Cao , Wang Yueh , Jeanette M. Roberts
发明人： Heidi B. Cao , Wang Yueh , Jeanette M. Roberts
IPC分类号： G03F7/039 , G03F7/38 , G03F7/30
CPC分类号： G03F7/0392 , G03F7/2004 , Y10S430/106
摘要： Numerous embodiments of a method to prevent outgassing from a low activation energy photoresist are described. In one embodiment of the present invention, a photoresist material is dispensed over a substrate to form a photoresist layer. The photoresist layer includes branched polymers coupled with acetal or ketal linkages. An exposed portion of the photoresist layer is exposed to a radiation treatment to cleave the acetal or ketal linkages and separate the branched polymers. The photoresist layer is baked at a temperature below about 100° C., and the separated branched polymers are too large to outgass from the photoresist layer.
摘要翻译：描述了防止从低活化能光致抗蚀剂脱气的方法的许多实施方案。在本发明的一个实施例中，将光致抗蚀剂材料分配在衬底上以形成光致抗蚀剂层。光致抗蚀剂层包括与缩醛或缩酮键连接的支链聚合物。将光致抗蚀剂层的暴露部分暴露于辐射处理以切割缩醛或缩酮键并分离支化聚合物。光致抗蚀剂层在低于约100℃的温度下烘烤，并且分离的支化聚合物太大而不能从光致抗蚀剂层逸出。

6. 发明授权

US09583389B2 Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) 有权
标题翻译：通过原子层沉积（ALD）和化学气相沉积（CVD）选择性地沉积金属膜
公开(公告)号：US09583389B2
公开(公告)日：2017-02-28
申请号：US14960104
申请日：2015-12-04
申请人： Patricio E. Romero , Scott B. Clendenning , Jeanette M. Roberts , Florian Gstrein
发明人： Patricio E. Romero , Scott B. Clendenning , Jeanette M. Roberts , Florian Gstrein
IPC分类号： H01L21/768 , H01L21/285 , C23C16/04 , C23C16/18 , C23C16/455
CPC分类号： H01L21/76897 , C23C16/04 , C23C16/18 , C23C16/45525 , H01L21/28506 , H01L21/28562 , H01L21/76801 , H01L21/76816 , H01L21/76838 , H01L21/76849 , H01L21/76879
摘要： Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.
摘要翻译：描述了通过原子层沉积（ALD）和化学气相沉积（CVD）来选择性地沉积金属膜。在一个示例中，制造用于集成电路的金属化结构的方法包括在衬底上形成暴露表面，暴露的表面包括暴露的介电材料的区域和暴露的金属的区域。该方法还涉及使用选择性金属沉积工艺在暴露的金属的区域上形成金属层，而不在暴露的电介质材料的区域上形成金属层。

7. 发明申请

US20160086850A1 SELECTIVE AREA DEPOSITION OF METAL FILMS BY ATOMIC LAYER DEPOSITION (ALD) AND CHEMICAL VAPOR DEPOSITION (CVD) 审中-公开
公开(公告)号：US20160086850A1
公开(公告)日：2016-03-24
申请号：US14960104
申请日：2015-12-04
申请人： Patricio E. Romero , Scott B. Clendenning , Jeanette M. Roberts , Florian Gstrein
发明人： Patricio E. Romero , Scott B. Clendenning , Jeanette M. Roberts , Florian Gstrein
IPC分类号： H01L21/768 , H01L21/285
CPC分类号： H01L21/76897 , C23C16/04 , C23C16/18 , C23C16/45525 , H01L21/28506 , H01L21/28562 , H01L21/76801 , H01L21/76816 , H01L21/76838 , H01L21/76849 , H01L21/76879
摘要： Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.

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