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1. 发明申请

US20060190668A1 Computer system architecture 有权
标题翻译：计算机系统架构
公开(公告)号：US20060190668A1
公开(公告)日：2006-08-24
申请号：US11064745
申请日：2005-02-24
申请人： Giora Biran , Matthew Cushing , Robert Drehmel , Allen Gavin , Mark Kautzman , Jamie Kuesel , Ming-I Lin , David Luick , James Marcella , Mark Maxson , Eric Mejdrich , Adam Muff , Clarence Ogilvie , Charles Woodruff
发明人： Giora Biran , Matthew Cushing , Robert Drehmel , Allen Gavin , Mark Kautzman , Jamie Kuesel , Ming-I Lin , David Luick , James Marcella , Mark Maxson , Eric Mejdrich , Adam Muff , Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4059
摘要： A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.
摘要翻译：高速计算机处理器系统具有用于图形处理器的高速接口。优选实施例将来自国际商业机器公司（IBM）的称为Giga-Processor Ultralite（GPUL）110的PowerPC微处理器与多芯片模块上的高速接口相结合。

2. 发明申请

US20050021921A1 Methods and systems for re-ordering commands to access memory 有权
标题翻译：用于重新排序命令以访问存储器的方法和系统
公开(公告)号：US20050021921A1
公开(公告)日：2005-01-27
申请号：US10625956
申请日：2003-07-24
申请人： Herman Blackmon , Joseph Kirscht , James Marcella , Brian Vanderpool
发明人： Herman Blackmon , Joseph Kirscht , James Marcella , Brian Vanderpool
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1631
摘要： Methods and systems for re-ordering commands to access memory are disclosed. Embodiments may receive a first command to access a memory bank of the memory and determine a penalty associated with the first command based upon a conflict with an access to the memory bank. The penalty, in many embodiments, may be calculated so the penalty expires when the memory bank and a data bus associated with the memory bank are available to process the first command. Then, the first command is queued and dispatched to an available sequencer after the penalty expires. After the first command is serviced, unexpired penalties of subsequent commands may be updated to reflect a conflict with the first command. Further embodiments select a command to dispatch from the commands with expired penalties, based upon priorities associated with the commands such as the order in which the commands were received and the command types.
摘要翻译：公开了将命令重新排序到访问存储器的方法和系统。实施例可以接收访问存储器的存储体的第一命令，并且基于与访问存储体的冲突来确定与第一命令相关联的惩罚。在许多实施例中，可以计算罚款，使得当与存储体相关联的存储体和数据总线可用于处理第一命令时，惩罚期满。然后，第一个命令排队，并在惩罚到期后发送到可用的序列器。在第一个命令被服务之后，可能会更新后续命令的未过期惩罚，以反映与第一个命令的冲突。另外的实施例基于与诸如命令的接收顺序和命令类型的命令相关联的优先级，选择从具有过期惩罚的命令分派的命令。

3. 发明申请

US20070189313A1 MULTI-NODE ARCHITECTURE WITH DAISY CHAIN COMMUNICATION LINK CONFIGURABLE TO OPERATE IN UNIDIRECTIONAL AND BIDIRECTIONAL MODES 失效
标题翻译：具有DAISY链式通信链路的多节点架构可配置为在单向和双向模式下运行
公开(公告)号：US20070189313A1
公开(公告)日：2007-08-16
申请号：US11740640
申请日：2007-04-26
申请人： Gerald Bartley , John Borkenhagen , Robert Drehmel , James Marcella
发明人： Gerald Bartley , John Borkenhagen , Robert Drehmel , James Marcella
IPC分类号： H04L12/56
CPC分类号： G06F13/364 , G06F11/2007 , G06F11/201
摘要： A circuit arrangement, method and apparatus utilize communication links that are selectively configurable to operate in both unidirectional and bidirectional modes to communicate data between multiple nodes that are interconnected to one another in a daisy chain configuration. As a result, in many instances communications may be maintained with nodes located both before and after a discontinuity in a daisy chain configuration.
摘要翻译：电路装置，方法和装置利用可选地配置为在单向和双向模式中操作的通信链路，以在菊花链配置中彼此互连的多个节点之间传送数据。结果，在许多情况下，可以维持在菊花链配置中的不连续之前和之后的节点的通信。

4. 发明申请

US20060075282A1 Diagnostic interface architecture for memory device 有权
公开(公告)号：US20060075282A1
公开(公告)日：2006-04-06
申请号：US10955735
申请日：2004-09-30
申请人： John Borkenhagen , William Hovis , James Marcella , Paul Rudrud
发明人： John Borkenhagen , William Hovis , James Marcella , Paul Rudrud
IPC分类号： G06F11/00
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/5602
摘要： A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.

5. 发明申请

US20060020740A1 Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes 有权
标题翻译：具有菊花链通信链路的多节点架构可配置为以单向和双向模式运行
公开(公告)号：US20060020740A1
公开(公告)日：2006-01-26
申请号：US10897341
申请日：2004-07-22
申请人： Gerald Bartley , John Borkenhagen , Robert Drehmel , James Marcella
发明人： Gerald Bartley , John Borkenhagen , Robert Drehmel , James Marcella
IPC分类号： G06F12/14
CPC分类号： G06F13/364 , G06F11/2007 , G06F11/201
摘要： A circuit arrangement, method and apparatus utilize communication links that are selectively configurable to operate in both unidirectional and bidirectional modes to communicate data between multiple nodes that are interconnected to one another in a daisy chain configuration. As a result, in many instances communications may be maintained with nodes located both before and after a discontinuity in a daisy chain configuration.
摘要翻译：电路装置，方法和装置利用可选地配置为在单向和双向模式中操作的通信链路，以在菊花链配置中彼此互连的多个节点之间传送数据。结果，在许多情况下，可以维持在菊花链配置中的不连续之前和之后的节点的通信。

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