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1. 发明授权

US08023144B2 Method for generating transposed image data 有权
标题翻译：用于生成转置图像数据的方法
公开(公告)号：US08023144B2
公开(公告)日：2011-09-20
申请号：US11456651
申请日：2006-07-11
申请人： Christopher Wilson Case , David A. Crutchfield , James Alan Ward
发明人： Christopher Wilson Case , David A. Crutchfield , James Alan Ward
IPC分类号： G06K15/00 , H04N1/405 , H04N1/46
CPC分类号： H04N1/40 , G06K15/10
摘要： A method for generating transposed image data for use in an imaging apparatus having access to a memory includes (a) generating a set of data blocks corresponding to at least a portion of image data representing an image to be printed; (b) performing a combined format and transpose operation on the set of data blocks; and (c) storing a result of the combined format and transpose operation in the memory.
摘要翻译：一种生成用于具有对存储器的访问的成像设备中的转置图像数据的方法，包括：（a）生成与表示要打印的图像的图像数据的至少一部分相对应的数据块集合; （b）对该组数据块执行组合格式和转置操作; 以及（c）将所述组合格式和转置操作的结果存储在所述存储器中。

2. 发明申请

US20080013119A1 Method for Generating Transposed Image Data 有权
标题翻译：生成转置图像数据的方法
公开(公告)号：US20080013119A1
公开(公告)日：2008-01-17
申请号：US11456651
申请日：2006-07-11
申请人： Christopher Wilson Case , David A. Crutchfield , James Alan Ward
发明人： Christopher Wilson Case , David A. Crutchfield , James Alan Ward
IPC分类号： G06K15/00
CPC分类号： H04N1/40 , G06K15/10
摘要： A method for generating transposed image data for use in an imaging apparatus having access to a memory includes (a) generating a set of data blocks corresponding to at least a portion of image data representing an image to be printed; (b) performing a combined format and transpose operation on the set of data blocks; and (c) storing a result of the combined format and transpose operation in the memory.
摘要翻译：一种生成用于具有对存储器的访问的成像设备中的转置图像数据的方法，包括：（a）生成与表示要打印的图像的图像数据的至少一部分相对应的数据块集合; （b）对该组数据块执行组合格式和转置操作; 以及（c）将所述组合格式和转置操作的结果存储在所述存储器中。

3. 发明授权

US07190473B1 Printer apparatus with integrated graphical user interface and method for using the same 有权
标题翻译：具有集成图形用户界面的打印机设备及其使用方法
公开(公告)号：US07190473B1
公开(公告)日：2007-03-13
申请号：US09610081
申请日：2000-07-05
申请人： Sherry Anderson Cook , Joseph Wade Luciano , John Anthony Moore , Brandon Lynn Satanek , James Alan Ward
发明人： Sherry Anderson Cook , Joseph Wade Luciano , John Anthony Moore , Brandon Lynn Satanek , James Alan Ward
IPC分类号： G06K15/02
CPC分类号： H04N1/00148 , G06K15/00 , H04N1/00132 , H04N1/00161 , H04N1/00167 , H04N1/00172 , H04N1/00188 , H04N1/00347 , H04N1/00538 , H04N1/6011 , H04N2201/0082 , H04N2201/0087 , H04N2201/0089
摘要： A stand-alone printing apparatus for transferring one or more digital photographs captured by a digital device to a printable medium. The printing apparatus includes an input member for receiving the digital photographs from a source and image processing for generating an image corresponding to each of the digital photographs. A graphical user interface with video display is integrated within the printing apparatus and includes a plurality of different states in which to preview the digital photograph images, select photographs for printing, and preview a printed page of selected photographs.
摘要翻译：一种用于将由数字设备捕获的一个或多个数字照片传送到可打印介质的独立打印设备。打印装置包括用于从源接收数字照片的输入构件和用于生成与每个数字照片相对应的图像的图像处理。具有视频显示的图形用户界面被集成在打印设备内，并且包括多个不同的状态，其中预览数字照片图像，选择用于打印的照片以及预览所选照片的打印页面。

4. 发明授权

US08254189B2 Method for tuning control signal associated with at least one memory device 有权
标题翻译：用于调谐与至少一个存储器件相关联的控制信号的方法
公开(公告)号：US08254189B2
公开(公告)日：2012-08-28
申请号：US12434375
申请日：2009-05-01
申请人： Nathan Wayne Foley , James Patrick Sharpe , James Alan Ward , Keith Allen Wahnsiedler
发明人： Nathan Wayne Foley , James Patrick Sharpe , James Alan Ward , Keith Allen Wahnsiedler
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/109 , G11C7/1093 , G11C2207/2254
摘要： Disclosed is a method for tuning control signals associated with one or more memory devices. The method includes performing a number of memory access operations on at least one memory device and recording results of the memory access operations. Specifically, the memory access operations are performed with different time delays for a first edge of a control signal. The control signal used for capturing data is provided by the at least one memory device. The method further includes selecting a time delay from the time delays used in the memory access operations. Moreover, the method includes utilizing the selected time delay in performing subsequent memory access operations on the at least one memory device. Also disclosed is a system including at least one memory device and an integrated circuit operatively coupled to the at least one memory device. The system incorporates the method for tuning control signals.
摘要翻译：公开了一种用于调谐与一个或多个存储器件相关联的控制信号的方法。该方法包括对至少一个存储器件执行多个存储器访问操作并记录存储器访问操作的结果。具体地，对于控制信号的第一边缘，以不同的时间延迟执行存储器存取操作。用于捕获数据的控制信号由至少一个存储设备提供。该方法还包括从存储器访问操作中使用的时间延迟中选择时间延迟。此外，该方法包括利用所选择的时间延迟来对至少一个存储器设备执行后续的存储器访问操作。还公开了一种包括至少一个存储器件和可操作地耦合到至少一个存储器件的集成电路的系统。该系统采用调谐控制信号的方法。

5. 发明授权

US09170901B2 System and method for analyzing an electronics device including a logic analyzer 有权
标题翻译：用于分析包括逻辑分析仪的电子设备的系统和方法
公开(公告)号：US09170901B2
公开(公告)日：2015-10-27
申请号：US13308286
申请日：2011-11-30
申请人： James Ray Bailey , Christopher W Case , James Patrick Sharpe , James Alan Ward , Michael Anthony Marra, III
发明人： James Ray Bailey , Christopher W Case , James Patrick Sharpe , James Alan Ward , Michael Anthony Marra, III
IPC分类号： G06F11/00 , G06F11/25 , G06F11/26 , G06F11/273 , G01R31/3177 , G06F11/22
CPC分类号： G06F11/25 , G01R31/3177 , G06F11/2294 , G06F11/26 , G06F11/273
摘要： A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.
摘要翻译：用于测试或调试具有嵌入式逻辑分析仪的被测器件的系统。在一个实施例中，系统包括存储在非瞬时存储器中的软件，用于测试具有嵌入式逻辑分析器的被测器件，该软件程序产品具有指令，当与被测器件相关联的计算设备执行时，该指令导致计算设备至少部分地基于在测试或调试会话期间由嵌入式逻辑分析器捕获的信号来重建被测器件中感兴趣的信号，并使计算设备向计算设备的用户显示感兴趣的重构信号。

6. 发明申请

US20110047424A1 INTEGRATED CIRCUIT INCLUDING A PROGRAMMABLE LOGIC ANALYZER WITH ENHANCED ANALYZING AND DEBUGGING CAPABILITES AND A METHOD THEREFOR 审中-公开
标题翻译：集成电路，包括具有增强分析和调试能力的可编程逻辑分析仪及其方法
公开(公告)号：US20110047424A1
公开(公告)日：2011-02-24
申请号：US12542976
申请日：2009-08-18
申请人： James Ray Bailey , James Alan Ward
发明人： James Ray Bailey , James Alan Ward
IPC分类号： G01R31/3177 , G06F11/00
CPC分类号： G06F11/2294
摘要： An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.
摘要翻译：一种集成电路，包括具有增强的分析和调试能力的逻辑分析仪及其方法。在本发明的一个实施例中，嵌入式逻辑分析器（ELA）从集成电路（IC）内的多个总线接收多个信号。 ELA包括互连模块，用于从多个接收信号中选择触发信号和/或采样信号。触发模块设置至少一个触发条件，并检测触发信号是否满足至少一个触发条件。当满足触发条件时，输出模块基于满足的至少一个触发条件来执行至少一个任务。如果由输出模块启动采样处理，则对采样的多个信号进行采样并将其存储在存储器中。输出模块执行多个用户定义任务的能力增强了ELA的调试能力，使其更加通用。

7. 发明申请

US20100277993A1 Method for Tuning Control Signal Associated with at Least One Memory Device 有权
标题翻译：用于调谐与至少一个存储器件相关的控制信号的方法
公开(公告)号：US20100277993A1
公开(公告)日：2010-11-04
申请号：US12434375
申请日：2009-05-01
申请人： Nathan Wayne Foley , James Patrick Sharpe , James Alan Ward , Keith Allen Wahnsiedler
发明人： Nathan Wayne Foley , James Patrick Sharpe , James Alan Ward , Keith Allen Wahnsiedler
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/109 , G11C7/1093 , G11C2207/2254
摘要： Disclosed is a method for tuning control signals associated with one or more memory devices. The method includes performing a number of memory access operations on at least one memory device and recording results of the memory access operations. Specifically, the memory access operations are performed with different time delays for a first edge of a control signal. The control signal used for capturing data is provided by the at least one memory device. The method further includes selecting a time delay from the time delays used in the memory access operations. Moreover, the method includes utilizing the selected time delay in performing subsequent memory access operations on the at least one memory device. Also disclosed is a system including at least one memory device and an integrated circuit operatively coupled to the at least one memory device. The system incorporates the method for tuning control signals.
摘要翻译：公开了一种用于调谐与一个或多个存储器件相关联的控制信号的方法。该方法包括对至少一个存储器件执行多个存储器访问操作并记录存储器访问操作的结果。具体地，对于控制信号的第一边缘，以不同的时间延迟执行存储器存取操作。用于捕获数据的控制信号由至少一个存储设备提供。该方法还包括从存储器访问操作中使用的时间延迟中选择时间延迟。此外，该方法包括利用所选择的时间延迟来对至少一个存储器设备执行后续的存储器访问操作。还公开了一种包括至少一个存储器件和可操作地耦合到至少一个存储器件的集成电路的系统。该系统采用调谐控制信号的方法。

8. 发明申请

US20120144256A1 System and Method for Analyzing an Electronics Device Including a Logic Analyzer 有权
标题翻译：用于分析包括逻辑分析仪的电子设备的系统和方法
公开(公告)号：US20120144256A1
公开(公告)日：2012-06-07
申请号：US13308286
申请日：2011-11-30
申请人： James Ray Bailey , Christopher W. Case , James Patrick Sharpe , James Alan Ward , Michael Anthony Marra, III
发明人： James Ray Bailey , Christopher W. Case , James Patrick Sharpe , James Alan Ward , Michael Anthony Marra, III
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/25 , G01R31/3177 , G06F11/2294 , G06F11/26 , G06F11/273
摘要： A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.
摘要翻译：用于测试或调试具有嵌入式逻辑分析仪的被测器件的系统。在一个实施例中，系统包括存储在非瞬时存储器中的软件，用于测试具有嵌入式逻辑分析器的被测器件，该软件程序产品具有指令，当与被测器件相关联的计算设备执行时，该指令导致计算设备至少部分地基于在测试或调试会话期间由嵌入式逻辑分析器捕获的信号来重建被测器件中感兴趣的信号，并使计算设备向计算设备的用户显示感兴趣的重构信号。

9. 发明授权

US06817697B2 Systems and methods for printhead architecture hardware formatting 有权
标题翻译：打印头架构硬件格式化的系统和方法
公开(公告)号：US06817697B2
公开(公告)日：2004-11-16
申请号：US10412825
申请日：2003-04-14
申请人： John Bates , David Allen Crutchfield , James Alan Ward
发明人： John Bates , David Allen Crutchfield , James Alan Ward
IPC分类号： B41J2205
CPC分类号： G06K15/00
摘要： The present invention is directed to systems and methods for formatting hardware for a printhead, for use in a printing device. The systems and methods of the present invention can support the formatting function with hardware formatting logic. This hardware formatting logic can support multiple printhead platforms. The hardware formatting logic of the present invention can perform bit shifting, resolution reduction, bit per pixel reduction, data masking for shingling, and input data sourcing. The present invention can also include a system processor further including an embedded ARM processor which can fetch and execute instructions and/or firmware. These instructions can direct the embedded processor to configure a format block included within the system processor. The format block can be configured by the system processor via one or more control registers.
摘要翻译：本发明涉及用于格式化用于打印装置的打印头的硬件的系统和方法。本发明的系统和方法可以用硬件格式化逻辑支持格式化功能。该硬件格式化逻辑可以支持多个打印头平台。本发明的硬件格式化逻辑可以执行位移位，分辨率降低，每像素减少位数，用于分页的数据屏蔽和输入数据采集。本发明还可以包括系统处理器，其还包括能够获取和执行指令和/或固件的嵌入式ARM处理器。这些指令可以指示嵌入式处理器配置系统处理器中包含的格式块。格式块可以由系统处理器通过一个或多个控制寄存器进行配置。

10. 发明授权

US07551323B2 Systems and methods for error diffusion 有权
标题翻译：错误扩散的系统和方法
公开(公告)号：US07551323B2
公开(公告)日：2009-06-23
申请号：US10414854
申请日：2003-04-16
申请人： James Ray Bailey , Curt Paul Breswick , David Allen Crutchfield , Ronald Edward Garnett , Bob Thai Pham , James Alan Ward
发明人： James Ray Bailey , Curt Paul Breswick , David Allen Crutchfield , Ronald Edward Garnett , Bob Thai Pham , James Alan Ward
IPC分类号： H04N1/56 , H04N1/60
CPC分类号： H04N1/52 , H04N1/4052
摘要： Error diffusion is performed upon input image data. In one aspect, multiple error diffusion processing elements perform error diffusion on a selected pixel in parallel. In another aspect, the error diffusion logic is integrally formed with a fast local memory in the same electronic device, such as an ASIC. The error data produced by the error diffusion logic for a pixel is buffered in the fast local memory until it is to be used by the error diffusion logic on other pixels. In still another aspect, a first-in-first-out (FIFO) buffer regulates or buffers the color image data between the output of a color conversion system, such as a colorant lookup table, and the input an error diffusion processing element. In yet another aspect, the error diffusion logic has tagging logic that produces and stores an indicator, either in the output data stream itself or in a separate area, to indicate whether a raster contains printable data.
摘要翻译：对输入图像数据执行误差扩散。在一个方面，多个误差扩散处理元件并行地对所选择的像素执行误差扩散。在另一方面，误差扩散逻辑与同一电子设备（例如ASIC）中的快速本地存储器整体形成。由像素的误差扩散逻辑产生的误差数据被缓冲在快速本地存储器中，直到其被其它像素上的误差扩散逻辑使用。在另一方面，先入先出（FIFO）缓冲器在诸如着色查找表的颜色转换系统的输出和输入误差扩散处理元件之间调节或缓冲彩色图像数据。在另一方面，误差扩散逻辑具有标记逻辑，该标签逻辑在输出数据流本身中或在单独的区域中产生和存储指示符，以指示光栅是否包含可打印数据。

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