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1. 发明申请

US20090257280A1 NAND FLASH MEMORY DEVICE AND METHOD OF OPERATING SAME 有权
标题翻译： NAND闪存存储器件及其操作方法
公开(公告)号：US20090257280A1
公开(公告)日：2009-10-15
申请号：US12405826
申请日：2009-03-17
申请人： Dong-Yean Oh , Woo-Kyung Lee , Jai Hyuk Song , Chang-Sub Lee
发明人： Dong-Yean Oh , Woo-Kyung Lee , Jai Hyuk Song , Chang-Sub Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/10
摘要： An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL , a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Ch1 from a second local channel Ch2. As the location i of the selected wordline WL increases close to the SST, the second channel potential Vch2 tends to increase excessively, causing errors. The excessive increase of Vch2 is prevented by modifying the voltages applied to string select lines (SSL) and/or to the bit lines (BL), or the pass voltages Vpass applied to the unselected wordlines (WL location i is equal or greater than a predetermined (stored) location number x. If incremental step pulse programming (ISPP) is implemented, the applied voltages are modified only if the ISPP loop count j is equal or greater than a predetermined (stored) critical loop number y.
摘要翻译：闪速存储器件包括一块NAND单元单元，该块中的每个NAND单元单元包括由多个n个字线控制的n个存储单元晶体管MC，并串联连接在连接到位线的串选择晶体管SST和接地选择晶体管GST。当编程电压Vpgm被施加到所选字线WL时，截止电压Vss被施加到靠近接地选择晶体管GST的附近未选字线，以将第一本地信道Ch1与第二本地信道Ch2隔离。当所选择的字线WL i的位置i增加到接近于SST时，第二通道电位Vch2会过度增加，导致错误。通过修改施加到串选择线（SSL）和/或位线（BL）的电压或施加到未选择字线（WL ），只有当所选择的字线WL i位置i等于或大于预定（存储的）位置号码x时。如果实现增量步进脉冲编程（ISPP），只有当ISPP循环计数j等于或大于预定（存储）的关键循环数y时，才施加电压。

2. 发明授权

US07589374B2 Semiconductor device and related fabrication method 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US07589374B2
公开(公告)日：2009-09-15
申请号：US11699990
申请日：2007-01-31
申请人： Jai-Hyuk Song , Jeong-Hyuk Choi , Woon-Kyung Lee
发明人： Jai-Hyuk Song , Jeong-Hyuk Choi , Woon-Kyung Lee
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11541
摘要： Embodiments of the invention provide a semiconductor device and a related method of fabricating a semiconductor device. In one embodiment, the invention provides a semiconductor device comprising a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor substrate, wherein the upper silicon pattern has the same crystal structure as the lower silicon pattern and the active region is defined by a device isolation layer. The semiconductor device further comprises a gate insulating layer disposed between the active region and the first gate electrode.
摘要翻译：本发明的实施例提供一种制造半导体器件的半导体器件和相关方法。在一个实施例中，本发明提供一种半导体器件，其包括第一栅电极，其包括下硅图案和上硅图案，并设置在半导体衬底的有源区上，其中上硅图案具有与下硅相同的晶体结构图案和有源区域由器件隔离层定义。半导体器件还包括设置在有源区和第一栅电极之间的栅极绝缘层。

3. 发明授权

US07560768B2 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07560768B2
公开(公告)日：2009-07-14
申请号：US11594808
申请日：2006-11-09
申请人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
发明人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.
摘要翻译：提供一种非易失性存储器件及其制造方法。非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。中间栅极图案和上部栅极图案之间的边界可以具有圆角。

4. 发明授权

US07494871B2 Semiconductor memory devices and methods for forming the same 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US07494871B2
公开(公告)日：2009-02-24
申请号：US11647671
申请日：2006-12-29
申请人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
发明人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.
摘要翻译：半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。绝缘层覆盖选择晶体管和单元晶体管。位线在绝缘层中并且电连接到相应的选择晶体管。沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。

5. 发明申请

US20090035906A1 Method of manufacturing a non-volatile semiconductor device 有权
标题翻译：制造非易失性半导体器件的方法
公开(公告)号：US20090035906A1
公开(公告)日：2009-02-05
申请号：US12222074
申请日：2008-08-01
申请人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
发明人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern.
摘要翻译：示例实施例涉及制造非易失性存储器件的方法。根据示例性实施例，制造非易失性存储器件的方法可以包括在衬底的上表面上形成至少一个栅极结构。至少一个栅极结构可以包括隧道绝缘层图案，电荷存储层图案，电介质层图案和控制栅极。根据示例实施例，制造非易失性存储器件的方法还可以包括在衬底的上表面上形成氮化硅层以覆盖至少一个栅极结构，在氮化硅层上形成绝缘中间层并且朝向基板的上表面和基板的下表面提供退火气体，以固化隧道绝缘层图案的缺陷。

6. 发明授权

US09824759B2 Non-volatile memory devices, memory systems, and methods of operating the same 有权
公开(公告)号：US09824759B2
公开(公告)日：2017-11-21
申请号：US14609072
申请日：2015-01-29
申请人： Dae-woong Kwon , Jai-hyuk Song , Chang-sub Lee
发明人： Dae-woong Kwon , Jai-hyuk Song , Chang-sub Lee
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： In a method of programming a non-volatile memory device, a first voltage is applied to a selected memory cell for programming, and a second voltage is applied to a non-selected memory cell. Before the second voltage rises to a predetermined voltage level, which is less than a program voltage level, the first voltage is greater than the second voltage or the second voltage is maintained at greater than a ground voltage level. Related non-volatile memory devices and memory systems are also discussed.

7. 发明授权

US08456918B2 NAND flash memory device and method of operating same to reduce a difference between channel potentials therein 有权
标题翻译： NAND闪存器件及其操作方法以减少其中的沟道电位之间的差异
公开(公告)号：US08456918B2
公开(公告)日：2013-06-04
申请号：US12405826
申请日：2009-03-17
申请人： Dong-Yean Oh , Woon-Kyung Lee , Jai Hyuk Song , Chang-Sub Lee
发明人： Dong-Yean Oh , Woon-Kyung Lee , Jai Hyuk Song , Chang-Sub Lee
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/10
摘要： An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL , a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Ch1 from a second local channel Ch2. As the location i of the selected wordline WL increases close to the SST, the second channel potential Vch2 tends to increase excessively, causing errors. The excessive increase of Vch2 is prevented by modifying the voltages applied to string select lines (SSL) and/or to the bit lines (BL), or the pass voltages Vpass applied to the unselected wordlines (WL location i is equal or greater than a predetermined (stored) location number x. If incremental step pulse programming (ISPP) is implemented, the applied voltages are modified only if the ISPP loop count j is equal or greater than a predetermined (stored) critical loop number y.
摘要翻译：闪速存储器件包括一块NAND单元单元，该块中的每个NAND单元单元包括由多个n个字线控制的n个存储单元晶体管MC，并串联连接在连接到位线的串选择晶体管SST和接地选择晶体管GST。当编程电压Vpgm被施加到所选字线WL时，截止电压Vss被施加到靠近接地选择晶体管GST的附近未选字线，以将第一本地信道Ch1与第二本地信道Ch2隔离。当所选择的字线WL i的位置i增加到接近于SST时，第二通道电位Vch2会过度增加，导致错误。通过修改施加到串选择线（SSL）和/或位线（BL）的电压或施加到未选择字线（WL ），只有当所选择的字线WL i位置i等于或大于预定（存储的）位置号码x时。如果实现增量步进脉冲编程（ISPP），只有当ISPP循环计数j等于或大于预定（存储）的关键循环数y时，才施加电压。

8. 发明申请

US20120318567A1 WIRING STRUCTURES 审中-公开
标题翻译：接线结构
公开(公告)号：US20120318567A1
公开(公告)日：2012-12-20
申请号：US13495216
申请日：2012-06-13
申请人： Jong-Hyun PARK , Jee-Yong KIM , Joon-Hee LEE , Jai-Hyuk SONG , Sang-Youn JO
发明人： Jong-Hyun PARK , Jee-Yong KIM , Joon-Hee LEE , Jai-Hyuk SONG , Sang-Youn JO
IPC分类号： H05K1/11 , H05K1/02 , H05K1/09
CPC分类号： H01L23/522 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A wiring structure includes a first plug extending through a first insulating interlayer on a substrate, a first wiring extending through a second insulating interlayer on the first insulating interlayer and the first wiring is electrically connected to the first plug, a diffusion barrier layer pattern on the first wiring and on the second insulating interlayer, a portion of the second insulating interlayer being free of being covered by the diffusion barrier layer pattern, a second plug extending through the diffusion barrier layer pattern, the second plug is in contact with the first wiring, and a second wiring electrically connected to the second plug.
摘要翻译：布线结构包括延伸穿过基板上的第一绝缘夹层的第一插塞，延伸穿过第一绝缘夹层上的第二绝缘夹层的第一布线和第一布线电连接到第一插头，扩散阻挡层图案第一布线并且在第二绝缘中间层上，第二绝缘中间层的一部分不被扩散阻挡层图案覆盖，延伸穿过扩散阻挡层图案的第二插塞，第二插塞与第一布线接触，以及电连接到第二插头的第二布线。

9. 发明申请

US20110222339A1 NONVOLATILE MEMORY DEVICE FOR REDUCING INTERFERENCE BETWEEN WORD LINES AND OPERATION METHOD THEREOF 失效
标题翻译：用于减少字线之间的干扰的非易失性存储器件及其操作方法
公开(公告)号：US20110222339A1
公开(公告)日：2011-09-15
申请号：US13044683
申请日：2011-03-10
申请人： Sung-Hoon Kim , Jai-Hyuk Song , Yong-Joon Choi
发明人： Sung-Hoon Kim , Jai-Hyuk Song , Yong-Joon Choi
IPC分类号： G11C16/28 , G11C16/10 , G11C16/08
CPC分类号： G11C16/3418 , G11C16/10 , G11C16/28
摘要： Provided are a nonvolatile memory device and a method of operating the same. The nonvolatile memory device in accordance with an embodiment of the inventive concept may include a string select line; a ground select line; a dummy word line adjacent to the ground select line; a first word line adjacent to the dummy word line; and a second word line disposed between the string select line and the first word line. The nonvolatile memory device is configured to apply a voltage to the dummy word line. When programming a memory cell connected to the first word line, a first dummy word line voltage lower than a voltage applied to the second word line is applied to the dummy word line. When programming a memory cell connected to the second word line, a second dummy word line voltage between a voltage applied to the first word line and the first dummy word line voltage is applied to the dummy word line. Accordingly, when a program operation is performed, a charge loss of a memory cell connected to a word line adjacent to a dummy word line can be reduced by changing a voltage applied to the dummy word line according to a select word line.
摘要翻译：提供一种非易失性存储器件及其操作方法。根据本发明构思的实施例的非易失性存储器件可以包括串选择线; 地选线; 与地面选择线相邻的虚拟字线; 与虚拟字线相邻的第一字线; 以及设置在所述串选择线和所述第一字线之间的第二字线。非易失性存储器件被配置为向虚拟字线施加电压。当编程连接到第一字线的存储单元时，低于施加到第二字线的电压的第一虚拟字线电压被施加到虚拟字线。当编程连接到第二字线的存储单元时，施加到第一字线的电压和第一虚拟字线电压之间的第二虚拟字线电压被施加到伪字线。因此，当执行编程操作时，可以通过根据选择字线改变施加到虚拟字线的电压来减少连接到与虚拟字线相邻的字线的存储单元的电荷损失。

10. 发明授权

US07867849B2 Method of manufacturing a non-volatile semiconductor device 有权
标题翻译：制造非易失性半导体器件的方法
公开(公告)号：US07867849B2
公开(公告)日：2011-01-11
申请号：US12222074
申请日：2008-08-01
申请人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
发明人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern.
摘要翻译：示例实施例涉及制造非易失性存储器件的方法。根据示例性实施例，制造非易失性存储器件的方法可以包括在衬底的上表面上形成至少一个栅极结构。至少一个栅极结构可以包括隧道绝缘层图案，电荷存储层图案，电介质层图案和控制栅极。根据示例实施例，制造非易失性存储器件的方法还可以包括在衬底的上表面上形成氮化硅层以覆盖至少一个栅极结构，在氮化硅层上形成绝缘中间层并且朝向基板的上表面和基板的下表面提供退火气体，以固化隧道绝缘层图案的缺陷。

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