专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09412583B2 Methods of forming dielectric layers and methods of manufacturing semiconductor devices using the same 有权
标题翻译：形成电介质层的方法和使用其制造半导体器件的方法
公开(公告)号：US09412583B2
公开(公告)日：2016-08-09
申请号：US13400952
申请日：2012-02-21
申请人： Sang-Yeol Kang , Suk-Jin Chung , Youn-Soo Kim , Jae-Hyoung Choi , Jae-Soon Lim , Min-Young Park
发明人： Sang-Yeol Kang , Suk-Jin Chung , Youn-Soo Kim , Jae-Hyoung Choi , Jae-Soon Lim , Min-Young Park
IPC分类号： H01L21/28 , H01L21/02 , H01L29/51 , H01L27/108 , H01L49/02 , H01L29/78
CPC分类号： H01L28/60 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02271 , H01L21/0228 , H01L21/28194 , H01L27/10808 , H01L27/10814 , H01L27/10855 , H01L28/40 , H01L29/517 , H01L29/78
摘要： To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.
摘要翻译：为了形成电介质层，有机金属前体被吸附在装载到处理室中的基板上。有机金属前体包括中心金属和与中心金属结合的配体。在基材上提供无活性氧化剂。无活性氧化剂与有机金属前体反应。活性氧化剂也提供到基底上。活性氧化剂的反应活性高于非活性氧化剂。

2. 发明授权

US07973352B2 Capacitors having composite dielectric layers containing crystallization inhibiting regions 有权
标题翻译：具有包含结晶抑制区域的复合电介质层的电容器
公开(公告)号：US07973352B2
公开(公告)日：2011-07-05
申请号：US12754713
申请日：2010-04-06
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L29/94
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

3. 发明申请

US20110095397A1 Semiconductor Structures Including Dielectric Layers and Capacitors Including Semiconductor Structures 审中-公开
标题翻译：包括介质层的半导体结构和包括半导体结构的电容器
公开(公告)号：US20110095397A1
公开(公告)日：2011-04-28
申请号：US12909289
申请日：2010-10-21
申请人： Suk-jin Chung , Jae-hyoung Choi , Youn-soo Kim , Jae-soon Lim , Sang-yeol Kang
发明人： Suk-jin Chung , Jae-hyoung Choi , Youn-soo Kim , Jae-soon Lim , Sang-yeol Kang
IPC分类号： H01L29/92 , H01G4/30
CPC分类号： H01L27/10852 , H01L21/02175 , H01L21/02183 , H01L21/02304 , H01L21/02362 , H01L28/40
摘要： Semiconductor structures including a first conductive layer; a dielectric layer on the first conductive layer; a second conductive layer on the dielectric layer; and a crystallized seed layer in at least one of a first portion between the first conductive layer and the dielectric layer and a second portion between the dielectric layer and the second conductive layer. Related capacitors and methods are also provided herein.
摘要翻译：包括第一导电层的半导体结构; 第一导电层上的电介质层; 介电层上的第二导电层; 以及在所述第一导电层和所述电介质层之间的第一部分中的至少一个中的结晶晶种层和所述介电层和所述第二导电层之间的第二部分。本文还提供了相关的电容器和方法。

4. 发明申请

US20110045183A1 METHODS OF FORMING A LAYER, METHODS OF FORMING A GATE STRUCTURE AND METHODS OF FORMING A CAPACITOR 审中-公开
标题翻译：形成层的方法，形成门结构的方法和形成电容器的方法
公开(公告)号：US20110045183A1
公开(公告)日：2011-02-24
申请号：US12704755
申请日：2010-02-12
申请人： Youn-Joung Cho , Youn-Soo Kim , Kyu-Ho Cho , Jung-Ho Lee , Jae-Hyoung Choi , Seung-Min Ryu
发明人： Youn-Joung Cho , Youn-Soo Kim , Kyu-Ho Cho , Jung-Ho Lee , Jae-Hyoung Choi , Seung-Min Ryu
IPC分类号： C23C16/06 , C23C16/44
CPC分类号： C23C16/18 , C23C16/405 , C23C16/45553 , H01L27/10852 , H01L28/40 , H01L28/91
摘要： In a method of forming a layer, a precursor including a metal and a ligand chelating to the metal is stabilized by contacting the precursor with an electron donating compound to provide a stabilized precursor onto a substrate. A reactant is introduced onto the substrate to bind to the metal in the stabilized precursor. The precursor stabilized by the electron donating compound has an improved thermal stability and thus the precursor is not dissociated at a high temperature atmosphere, and the layer having a uniform thickness is formed on the substrate.
摘要翻译：在形成层的方法中，通过使前体与给电子化合物接触来使包含金属和与金属螯合的配体的前体稳定化，以将稳定的前体提供到基底上。将反应物引入到底物上以与稳定的前体中的金属结合。通过给电子化合物稳定的前体具有改善的热稳定性，因此前体在高温气氛下不解离，并且在基板上形成具有均匀厚度的层。

5. 发明授权

US07723770B2 Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions 有权
标题翻译：集成电路电容器，其中包含结晶抑制区的复合介电层
公开(公告)号：US07723770B2
公开(公告)日：2010-05-25
申请号：US11210332
申请日：2005-08-24
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L27/108
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

6. 发明申请

US20100117194A1 METAL-INSULATOR-METAL CAPACITORS WITH A CHEMICAL BARRIER LAYER IN A LOWER ELECTRODE 审中-公开
标题翻译：金属绝缘体 - 金属电容器，在较低的电极中具有化学障碍层
公开(公告)号：US20100117194A1
公开(公告)日：2010-05-13
申请号：US12639184
申请日：2009-12-16
申请人： Eun-ae Chung , Jae-hyoung Choi , Jung-hee Chung , Young-sun Kim , Cha-young Yoo
发明人： Eun-ae Chung , Jae-hyoung Choi , Jung-hee Chung , Young-sun Kim , Cha-young Yoo
IPC分类号： H01L29/92 , H01G4/06 , H01G4/008
CPC分类号： H01L21/7687 , H01L27/10852 , H01L28/65 , H01L28/75
摘要： A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.
摘要翻译：金属绝缘体金属（MIM）电容器包括下电极，电介质层和上电极。下电极包括第一导电层，第一导电层上的化学阻挡层和化学阻挡层上的第二导电层。化学屏障层位于第一和第二导电层之间，并且是与第一和第二导电层不同的材料。介电层位于下电极上。上电极位于与下电极相对的电介质层上。第一和第二导电层可以具有相同的厚度。化学阻挡层可以比第一和第二导电层中的每一个薄。讨论相关方法。

7. 发明授权

US07422943B2 Semiconductor device capacitors with oxide-nitride layers and methods of fabricating such capacitors 有权
标题翻译：具有氧化物氮化物层的半导体器件电容器和制造这种电容器的方法
公开(公告)号：US07422943B2
公开(公告)日：2008-09-09
申请号：US11386660
申请日：2006-03-22
申请人： Jong-cheol Lee , Young-sun Kim , Jung-hee Chung , Jae-hyoung Choi , Se-hoon Oh , Hong-bum Park
发明人： Jong-cheol Lee , Young-sun Kim , Jung-hee Chung , Jae-hyoung Choi , Se-hoon Oh , Hong-bum Park
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/75
摘要： Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer is nitridized.
摘要翻译：提供具有包括下电极，电介质层和包括导电金属氮化物层和掺杂多晶硅锗层的上电极的上电极的电容器。导电金属氮化物层的至少一部分被氧化和/或至少部分介电层被氮化。

8. 发明授权

US07304367B2 Metal-insulator-metal capacitors including transition metal silicide films on doped polysilicon contact plugs 有权
标题翻译：金属绝缘体金属电容器，包括掺杂多晶硅接触插头上的过渡金属硅化物膜
公开(公告)号：US07304367B2
公开(公告)日：2007-12-04
申请号：US10870745
申请日：2004-06-17
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
IPC分类号： H01L29/00
CPC分类号： H01L28/91
摘要： A MIM capacitor can include a doped polysilicon contact plug in an interlayer insulating film. A lower electrode of the MIM capacitor includes a transition metal nitride film is on the doped polysilicon contact plug. A transition metal silicide film is between the doped polysilicon contact plug and the transition metal nitride film.
摘要翻译： MIM电容器可以包括层间绝缘膜中的掺杂多晶硅接触插塞。 MIM电容器的下电极包括在掺杂多晶硅接触插塞上的过渡金属氮化物膜。过渡金属硅化物膜位于掺杂多晶硅接触插塞和过渡金属氮化物膜之间。

9. 发明申请

US20070099419A1 Methods for forming semiconductor devices including thermal processing 有权
公开(公告)号：US20070099419A1
公开(公告)日：2007-05-03
申请号：US11641138
申请日：2006-12-19
申请人： Jae-hyoung Choi , Wan-don Kim , Cha-young Yoo , Suk-jin Chung
发明人： Jae-hyoung Choi , Wan-don Kim , Cha-young Yoo , Suk-jin Chung
IPC分类号： H01L21/44
CPC分类号： H01L28/65 , H01L28/40
摘要： Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.

10. 发明申请

US20070099379A1 Method of manufacturing a dielectric film in a capacitor 失效
标题翻译：制造电容器中的电介质膜的方法
公开(公告)号：US20070099379A1
公开(公告)日：2007-05-03
申请号：US11544760
申请日：2006-10-10
申请人： Jae-hyoung Choi , Sung-ho Kang , Jung-hee Chung , Seog-min Lee , Jong-bom Seo , Young-min Kim
发明人： Jae-hyoung Choi , Sung-ho Kang , Jung-hee Chung , Seog-min Lee , Jong-bom Seo , Young-min Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/0228 , C23C16/405 , C23C16/45527 , H01L21/02175 , H01L21/3141 , H01L21/31645 , H01L28/40
摘要： A method of manufacturing a dielectric layer for a capacitor including sequentially supplying and purging a first and a second precursor material for a first and a second predetermined amount of time, respectively, in an initial cycle, sequentially supplying and purging the first and the second precursor materials for a third predetermined amount of time, which is shorter than the first and/or second predetermined amount of time, in a post cycle, which follows the initial cycle, and repeating the initial and post cycles to form a dielectric layer having a predetermined thickness.
摘要翻译：一种电容器用电介质层的制造方法，其特征在于，在初始循环中分别顺序地供给和吹扫第一和第二前体材料，分别第一和第二预定量的时间，依次供给和净化所述第一和第二前体在后循环中第三预定时间量的材料，其比第一和/或第二预定量的时间短，其在初始循环之后，并且重复初始和后期循环以形成具有预定的厚度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式