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1. 发明申请

US20100164442A1 DYNAMIC ADJUSTMENT OF POWER CONVERTER CONTROL 审中-公开
标题翻译：动力转换器控制的动态调整
公开(公告)号：US20100164442A1
公开(公告)日：2010-07-01
申请号：US12347780
申请日：2008-12-31
申请人： Omer Vikinski , Jae-Hong Hahn , Kobi Littman
发明人： Omer Vikinski , Jae-Hong Hahn , Kobi Littman
IPC分类号： G05F1/10
CPC分类号： H02M3/156
摘要： In general, in one aspect, the disclosure describes a system comprising a power converter, a power delivery network, a load, and a communication link between the power converter and the load. The communication link is to implement a training sequence to dynamically adjust parameters of the power converter and set load-line slope based on implementation of the system. The load includes a training capability to generate stimuli having defined patterns and to update on the stimuli application to the power converter over the communication link. The power converter includes a controller to measure noise amplitude in a power output based on the stimuli, to adjust loop parameters to reduce the noise amplitude, and to set the load-line for the power converter based on the adjusting.
摘要翻译：通常，在一方面，本公开描述了一种包括功率转换器，功率传递网络，负载以及功率转换器和负载之间的通信链路的系统。通信链路是实施训练序列，动态调整功率转换器的参数，并根据系统的实现设置负载线斜率。负载包括产生具有限定模式的刺激的训练能力，并且通过通信链路更新对功率转换器的刺激应用。功率转换器包括控制器，用于基于该刺激来测量功率输出中的噪声幅度，以调整环路参数以减小噪声幅度，并且基于调整来设置功率转换器的负载线。

2. 发明申请

US20080001693A1 Configurable multiphase coupled magnetic structure 失效
标题翻译：可配置多相耦合磁结构
公开(公告)号：US20080001693A1
公开(公告)日：2008-01-03
申请号：US11478188
申请日：2006-06-29
申请人： Jae-Hong Hahn , Jorge Rodriguez , Don Nguyen
发明人： Jae-Hong Hahn , Jorge Rodriguez , Don Nguyen
IPC分类号： H01F27/02
CPC分类号： H01F30/12 , H01F3/12 , H01F27/26 , H01F27/346
摘要： In some embodiments, a configurable multiphase coupled magnetic structure may include a four-sided pot core defining an interior space, one or more cylindrical cores disposed within the interior space of the four-sided pot core, and at least two windings respectively wound around the one or more cylindrical cores, wherein the at least two windings are connected in a multiphase power delivery configuration. The windings may be multi-turn windings. The four-sided pot core may be a rectangular-shaped pot core. The cylindrical cores may be I-cores. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，可配置的多相耦合磁性结构可以包括限定内部空间的四边框芯，设置在四边框芯的内部空间内的一个或多个圆柱形芯，以及分别围绕一个或多个圆柱形芯，其中所述至少两个绕组以多相电力输送配置连接。绕组可以是多匝绕组。四面盆芯可以是矩形罐芯。圆柱形芯可以是I型芯。公开和要求保护其他实施例。

3. 发明授权

US06801026B2 Hysteretic DC-DC converters 有权
公开(公告)号：US06801026B2
公开(公告)日：2004-10-05
申请号：US10326738
申请日：2002-12-20
申请人： Gerhard Schrom , Jae-Hong Hahn , Peter Hazucha
发明人： Gerhard Schrom , Jae-Hong Hahn , Peter Hazucha
IPC分类号： G05F159
CPC分类号： H02M3/156 , H02M3/1584 , H02M2003/1586
摘要： According to some embodiments, a plurality of single-phase hysteretic converters operate in accordance with associated synchronization signals.

4. 发明申请

US20080238378A1 Voltage regulator 审中-公开
标题翻译：电压调节器
公开(公告)号：US20080238378A1
公开(公告)日：2008-10-02
申请号：US11731789
申请日：2007-03-30
申请人： Alexander Uan-Zo-li , Jae-Hong Hahn
发明人： Alexander Uan-Zo-li , Jae-Hong Hahn
IPC分类号： G05F1/46
CPC分类号： H02M3/1584 , H02M2001/0032 , H02M2003/1586 , Y02B70/16
摘要： In some embodiments, a voltage regulator assembly comprises a first voltage regulator circuit selectively coupled to a first input voltage and comprising a first inductor, a second regulator circuit selectively coupled to the first input voltage and comprising a second inductor to inductively couple the second regulator circuit to the first voltage regulator circuit, a bypass switch coupled to the second regulator circuit, and a controller coupled to the bypass switch comprising logic to activate the bypass switch when a load on the voltage regulator assembly falls below a threshold. Other embodiments may be described.
摘要翻译：在一些实施例中，电压调节器组件包括选择性地耦合到第一输入电压并包括第一电感器的第一调压器电路，选择性地耦合到第一输入电压的第二调节器电路，并且包括第二电感器以感应耦合第二调节器电路耦合到第二调节器电路的旁路开关以及耦合到旁路开关的控制器，该旁路开关包括当电压调节器组件上的负载下降到阈值以下时启动旁路开关的逻辑。可以描述其他实施例。

5. 发明申请

US20050146356A1 Driver circuit 失效
标题翻译：驱动电路
公开(公告)号：US20050146356A1
公开(公告)日：2005-07-07
申请号：US10749928
申请日：2003-12-29
申请人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek De
发明人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek De
IPC分类号： H03K17/691 , H03K19/00 , H03K19/0175
CPC分类号： H03K17/691 , H03K19/0013
摘要： A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.
摘要翻译：电路包括第一驱动器，第二驱动器和耦合到第一和第二驱动器的变压器。在操作中，第一驱动器从第一输入端口接收第一信号，第二驱动器从第二输入端口接收第一信号的时间延迟版本，并且变压器向输出端口提供输出信号。一种方法包括接收第一输入信号，接收第二输入信号，然后处理第一输入信号和第二输入信号。第二输入信号是第一输入信号的时间延迟版本，第一输入信号和第二输入信号的处理产生半升余弦信号。

6. 发明授权

US07015720B2 Driver circuit 失效
标题翻译：驱动电路
公开(公告)号：US07015720B2
公开(公告)日：2006-03-21
申请号：US10749928
申请日：2003-12-29
申请人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek K. De
发明人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek K. De
IPC分类号： H03K19/0175
CPC分类号： H03K17/691 , H03K19/0013
摘要： A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.
摘要翻译：电路包括第一驱动器，第二驱动器和耦合到第一和第二驱动器的变压器。在操作中，第一驱动器从第一输入端口接收第一信号，第二驱动器从第二输入端口接收第一信号的时间延迟版本，并且变压器向输出端口提供输出信号。一种方法包括接收第一输入信号，接收第二输入信号，然后处理第一输入信号和第二输入信号。第二输入信号是第一输入信号的时间延迟版本，第一输入信号和第二输入信号的处理产生半升余弦信号。

7. 发明授权

US07733204B2 Configurable multiphase coupled magnetic structure 失效
标题翻译：可配置多相耦合磁结构
公开(公告)号：US07733204B2
公开(公告)日：2010-06-08
申请号：US11478188
申请日：2006-06-29
申请人： Jae-Hong Hahn , Jorge Rodrignez , Don Nguyen
发明人： Jae-Hong Hahn , Jorge Rodrignez , Don Nguyen
IPC分类号： H01F27/02
CPC分类号： H01F30/12 , H01F3/12 , H01F27/26 , H01F27/346
摘要： In some embodiments, a configurable multiphase coupled magnetic structure may include a four-sided pot core defining an interior space, one or more cylindrical cores disposed within the interior space of the four-sided pot core, and at least two windings respectively wound around the one or more cylindrical cores, wherein the at least two windings are connected in a multiphase power delivery configuration. The windings may be multi-turn windings. The four-sided pot core may be a rectangular-shaped pot core. The cylindrical cores may be I-cores. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，可配置的多相耦合磁性结构可以包括限定内部空间的四边框芯，设置在四边框芯的内部空间内的一个或多个圆柱形芯，以及分别围绕一个或多个圆柱形芯，其中所述至少两个绕组以多相电力输送配置连接。绕组可以是多匝绕组。四面盆芯可以是矩形罐芯。圆柱形芯可以是I型芯。公开和要求保护其他实施例。

8. 发明申请

US20070052446A1 DRIVER CIRCUIT 有权
标题翻译：驱动电路
公开(公告)号：US20070052446A1
公开(公告)日：2007-03-08
申请号：US11277117
申请日：2006-03-21
申请人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek De
发明人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek De
IPC分类号： H03K19/0175
CPC分类号： H03K17/691 , H03K19/0013
摘要： A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.
摘要翻译：电路包括第一驱动器，第二驱动器和耦合到第一和第二驱动器的变压器。在操作中，第一驱动器从第一输入端口接收第一信号，第二驱动器从第二输入端口接收第一信号的时间延迟版本，并且变压器向输出端口提供输出信号。一种方法包括接收第一输入信号，接收第二输入信号，然后处理第一输入信号和第二输入信号。第二输入信号是第一输入信号的时间延迟版本，第一输入信号和第二输入信号的处理产生半升余弦信号。

9. 发明授权

US07358770B2 Driver circuit 有权
标题翻译：驱动电路
公开(公告)号：US07358770B2
公开(公告)日：2008-04-15
申请号：US11277117
申请日：2006-03-21
申请人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek K. De
发明人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek K. De
IPC分类号： H03K19/0175
CPC分类号： H03K17/691 , H03K19/0013
摘要： A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.
摘要翻译：电路包括第一驱动器，第二驱动器和耦合到第一和第二驱动器的变压器。在操作中，第一驱动器从第一输入端口接收第一信号，第二驱动器从第二输入端口接收第一信号的时间延迟版本，并且变压器向输出端口提供输出信号。一种方法包括接收第一输入信号，接收第二输入信号，然后处理第一输入信号和第二输入信号。第二输入信号是第一输入信号的时间延迟版本，第一输入信号和第二输入信号的处理产生半升余弦信号。

10. 发明授权

US06798256B1 Resonant buffer apparatus, method, and system 有权
标题翻译：共振缓冲装置，方法和系统
公开(公告)号：US06798256B1
公开(公告)日：2004-09-28
申请号：US10426606
申请日：2003-04-30
申请人： Peter Hazucha , Gerhard Schrom , Jae-Hong Hahn
发明人： Peter Hazucha , Gerhard Schrom , Jae-Hong Hahn
IPC分类号： H03B100
CPC分类号： H03K19/0019 , H03K17/04163 , H03K17/163 , H03K2217/009
摘要： A buffer circuit includes a resonant circuit. An output of the resonant buffer circuit transitions once for three transitions on an input.
摘要翻译：缓冲电路包括谐振电路。谐振缓冲电路的输出在输入上转换三次转换。

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