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1. 发明授权

US07873858B2 Clock signal generation device and method 有权
标题翻译：时钟信号发生装置及方法
公开(公告)号：US07873858B2
公开(公告)日：2011-01-18
申请号：US11775541
申请日：2007-07-10
申请人： Hyuk-Jun Sung , Chan-Yong Kim , Jong-Pil Cho
发明人： Hyuk-Jun Sung , Chan-Yong Kim , Jong-Pil Cho
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A clock signal generator for a USB device. The clock signal generator includes a control circuit and a clock generator that does not need to include a crystal oscillator. The control circuit counts the cycle of the clock signal during the period between two sync signals successively inputted, and generates a frequency control signal corresponding to the count value. The clock generator generates the clock signal with a frequency corresponding to the frequency control signal. The clock signal generator can generate a clock signal that is suitable for the data transfer rate defined, in the USB specification. In addition, the clock; signal generator can generate an RX clock signal so that an RX data signal can be recovered with its energy being stable.
摘要翻译： USB设备的时钟信号发生器。时钟信号发生器包括不需要包括晶体振荡器的控制电路和时钟发生器。控制电路在连续输入的两个同步信号之间的周期内对时钟信号的周期进行计数，并产生与计数值对应的频率控制信号。时钟发生器产生具有对应于频率控制信号的频率的时钟信号。时钟信号发生器可以产生适合于在USB规范中定义的数据传输速率的时钟信号。另外，时钟; 信号发生器可以产生RX时钟信号，使得RX数据信号能够以其能量稳定地恢复。

2. 发明申请

US20100231293A1 APPARATUS FOR TYPE-A DEMODULATION AND INTEGRATED CIRCUIT CARD INCLUDING THE SAME 有权
标题翻译：用于类型A解调和集成电路卡的装置，包括它们
公开(公告)号：US20100231293A1
公开(公告)日：2010-09-16
申请号：US12722812
申请日：2010-03-12
申请人： Jong Pil Cho , Hyuk Jun Sung
发明人： Jong Pil Cho , Hyuk Jun Sung
IPC分类号： H03D1/00
CPC分类号： H03D1/06
摘要： A type-A demodulator comprising a first rectifier configured to rectify a radio frequency (RF) signal received through an antenna and output a first voltage, a second rectifier configured to rectify the voltage of the RF signal received through the antenna and output a second voltage having a different voltage level than the first voltage, and a pause data detector configured to compare the first voltage with the second voltage and detect received pause data.
摘要翻译：一种A型解调器，包括：第一整流器，被配置为对通过天线接收的射频（RF）信号进行整流并输出第一电压;第二整流器，被配置为对通过天线接收的RF信号的电压进行整流，并输出第二电压具有与所述第一电压不同的电压电平，以及暂停数据检测器，被配置为将所述第一电压与所述第二电压进行比较并检测接收到的暂停数据。

3. 发明申请

US20070047688A1 Frequency detecting circuit and method, and semiconductor apparatus including frequency detecting circuit 有权
标题翻译：频率检测电路和方法，以及包括频率检测电路的半导体装置
公开(公告)号：US20070047688A1
公开(公告)日：2007-03-01
申请号：US11507771
申请日：2006-08-22
申请人： Hyuk-Jun Sung , Ki-Bum Nam
发明人： Hyuk-Jun Sung , Ki-Bum Nam
IPC分类号： H03D3/24
CPC分类号： H03D13/001
摘要： A frequency detecting circuit and method and a semiconductor apparatus including the frequency detecting circuit, in which the frequency detecting circuit includes an edge detecting circuit, a clock signal generating circuit, and a determination circuit. The edge detecting circuit detects an edge of an input clock signal. The clock signal generating circuit generates a selection clock signal, which is a periodic pulse signal, in response to the detected edge. The determination circuit generates a frequency detection signal based on the number of occurrences of the selection clock signal in a period of the clock signal. The semiconductor apparatus includes the above-described frequency detecting circuit and a processor resetting the semiconductor apparatus in response to the frequency detection signal. Since a frequency is detected every half period, that is every high/low level period, of the clock signal in a digital manner, the reliability and the accuracy of frequency detection is improved.
摘要翻译：频率检测电路和方法以及包括频率检测电路的半导体装置，其中频率检测电路包括边缘检测电路，时钟信号发生电路和确定电路。边缘检测电路检测输入时钟信号的边沿。时钟信号发生电路响应于检测到的边沿而产生作为周期脉冲信号的选择时钟信号。确定电路根据时钟信号的周期内的选择时钟信号的出现次数生成频率检测信号。半导体装置包括上述频率检测电路和响应于该频率检测信号而重置半导体装置的处理器。由于以数字方式每半个周期（即每个高/低电平周期）检测频率，所以提高了频率检测的可靠性和精度。

4. 发明授权

US07454633B2 Integrated circuit card for reducing power consumption 有权
标题翻译：集成电路卡，用于降低功耗
公开(公告)号：US07454633B2
公开(公告)日：2008-11-18
申请号：US11204814
申请日：2005-08-16
申请人： Hyuk-Jun Sung , Ki-Yeol Kim
发明人： Hyuk-Jun Sung , Ki-Yeol Kim
IPC分类号： G06F1/00 , G06F1/26 , G06K5/00 , G06K19/06
CPC分类号： G06K19/0716 , G06K19/0707 , G06K19/0712 , G06K19/0723 , G06K19/073
摘要： An integrated circuit card includes an interface block for performing an interface function with the external devices and a power controller for controlling power of a security integrated circuit for detecting if an operational environment is in an abnormal state, the power controller periodically and selectively applies power to the security integrated circuit. Thus, power consumption is reduced in the integrated circuit card; and a stable operation of the integrated circuit card which contactlessly communicates with the external devices can be secured with an extended communication distance.
摘要翻译：集成电路卡包括用于与外部设备进行接口功能的接口块和用于控制安全集成电路的功率的功率控制器，用于检测操作环境是否处于异常状态，功率控制器周期性地选择性地将功率施加到安全集成电路。因此，集成电路卡中的功耗降低; 并且能够以延长的通信距离确保与外部设备无接触地通信的集成电路卡的稳定操作。

5. 发明授权

US08038071B2 Smart card system and driving method thereof 有权
标题翻译：智能卡系统及其驱动方法
公开(公告)号：US08038071B2
公开(公告)日：2011-10-18
申请号：US12397579
申请日：2009-03-04
申请人： Hyuk-Jun Sung
发明人： Hyuk-Jun Sung
IPC分类号： G06K19/06
CPC分类号： G06K19/0723 , G06F1/08 , G06K7/0008
摘要： A smart card system may include a smart card; and a smart card reader configured to communicate via a smart card protocol with the smart card, wherein the smart card includes a modulus counter that generates an operation clock of the smart card by receiving an external clock complying with the smart card protocol from the smart card reader, dividing the external clock a first and a second time to generate a first and a second dividing clock, counting the first dividing clock for A number of times, and counting the second dividing clock for N-A number of times.
摘要翻译：智能卡系统可以包括智能卡; 以及智能卡读取器，被配置为经由智能卡协议与智能卡通信，其中智能卡包括模数计数器，其通过从智能卡接收符合智能卡协议的外部时钟来生成智能卡的操作时钟读取器，第一次和第二次分频外部时钟以产生第一和第二分频时钟，对第一分频时钟进行A次计数，并对第二分频时钟进行NA次数的计数。

6. 发明授权

US07493510B2 Clock signal generator circuit for serial bus communication 有权
标题翻译：时钟信号发生器电路，用于串行总线通讯
公开(公告)号：US07493510B2
公开(公告)日：2009-02-17
申请号：US11091427
申请日：2005-03-28
申请人： Hyuk-Jun Sung , Chan-Yong Kim
发明人： Hyuk-Jun Sung , Chan-Yong Kim
IPC分类号： G06F1/08
CPC分类号： H03L7/0995 , G06F1/04 , G06F1/08 , H03L7/1976
摘要： Provided is a smart card for communicating with a host computer through a universal serial bus (USB). The smart card includes an internal clock signal generator to generate an internal clock signal, a period detector to detect a period of the internal clock signal and to generate a control code according to the detected period, and a transmission clock generator to generate a transmission clock signal which varies from the internal clock signal according to the control code. The smart card transfers data in sync with the transmission clock signal.
摘要翻译：提供了一种用于通过通用串行总线（USB）与主机通信的智能卡。智能卡包括内部时钟信号发生器以产生内部时钟信号，周期检测器，用于检测内部时钟信号的周期并根据检测到的周期产生控制码;传输时钟发生器，用于产生传输时钟信号根据控制码从内部时钟信号变化。智能卡与传输时钟信号同步传输数据。

7. 发明申请

US20050216780A1 Clock signal generator circuit for serial bus communication 有权
标题翻译：时钟信号发生器电路，用于串行总线通讯
公开(公告)号：US20050216780A1
公开(公告)日：2005-09-29
申请号：US11091427
申请日：2005-03-28
申请人： Hyuk-Jun Sung , Chan-Yong Kim
发明人： Hyuk-Jun Sung , Chan-Yong Kim
IPC分类号： G06F1/04 , G06F1/08 , G06F13/38 , G06K7/08 , G06K19/07 , H03K3/02 , H03L7/099 , H03L7/197
CPC分类号： H03L7/0995 , G06F1/04 , G06F1/08 , H03L7/1976
摘要： Provided is a smart card for communicating with a host computer through a universal serial bus (USB). The smart card includes an internal clock signal generator to generate an internal clock signal, a period detector to detect a period of the internal clock signal and to generate a control code according to the detected period, and a transmission clock generator to generate a transmission clock signal which varies from the internal clock signal according to the control code. The smart card transfers data in sync with the transmission clock signal.
摘要翻译：提供了一种用于通过通用串行总线（USB）与主机通信的智能卡。智能卡包括内部时钟信号发生器以产生内部时钟信号，周期检测器，用于检测内部时钟信号的周期并根据检测到的周期产生控制码;传输时钟发生器，用于产生传输时钟信号根据控制码从内部时钟信号变化。智能卡与传输时钟信号同步传输数据。

8. 发明授权

US07801259B2 Frequency detecting circuit and method, and semiconductor apparatus including frequency detecting circuit 有权
标题翻译：频率检测电路和方法，以及包括频率检测电路的半导体装置
公开(公告)号：US07801259B2
公开(公告)日：2010-09-21
申请号：US11507771
申请日：2006-08-22
申请人： Hyuk-Jun Sung , Ki-Bum Nam
发明人： Hyuk-Jun Sung , Ki-Bum Nam
IPC分类号： H04L7/04
CPC分类号： H03D13/001
摘要： A frequency detecting circuit and method and a semiconductor apparatus including the frequency detecting circuit, in which the frequency detecting circuit includes an edge detecting circuit, a clock signal generating circuit, and a determination circuit. The edge detecting circuit detects an edge of an input clock signal. The clock signal generating circuit generates a selection clock signal, which is a periodic pulse signal, in response to the detected edge. The determination circuit generates a frequency detection signal based on the number of occurrences of the selection clock signal in a period of the clock signal. The semiconductor apparatus includes the above-described frequency detecting circuit and a processor resetting the semiconductor apparatus in response to the frequency detection signal. Since a frequency is detected every half period, that is every high/low level period, of the clock signal in a digital manner, the reliability and the accuracy of frequency detection is improved.
摘要翻译：频率检测电路和方法以及包括频率检测电路的半导体装置，其中频率检测电路包括边缘检测电路，时钟信号发生电路和确定电路。边缘检测电路检测输入时钟信号的边沿。时钟信号发生电路响应于检测到的边沿而产生作为周期脉冲信号的选择时钟信号。确定电路根据时钟信号的周期内的选择时钟信号的出现次数生成频率检测信号。半导体装置包括上述频率检测电路和响应于该频率检测信号而重置半导体装置的处理器。由于以数字方式每半个周期（即每个高/低电平周期）检测频率，所以提高了频率检测的可靠性和精度。

9. 发明申请

US20090224046A1 SMART CARD SYSTEM AND DRIVING METHOD THEREOF 有权
标题翻译：智能卡系统及其驱动方法
公开(公告)号：US20090224046A1
公开(公告)日：2009-09-10
申请号：US12397579
申请日：2009-03-04
申请人： Hyuk-Jun Sung
发明人： Hyuk-Jun Sung
IPC分类号： G06K7/00
CPC分类号： G06K19/0723 , G06F1/08 , G06K7/0008
摘要： A smart card system may include a smart card; and a smart card reader configured to communicate via a smart card protocol with the smart card, wherein the smart card includes a modulus counter that generates an operation clock of the smart card by receiving an external clock complying with the smart card protocol from the smart card reader, dividing the external clock a first and a second time to generate a first and a second dividing clock, counting the first dividing clock for A number of times, and counting the second dividing clock for N−A number of times.
摘要翻译：智能卡系统可以包括智能卡; 以及智能卡读取器，被配置为经由智能卡协议与智能卡通信，其中智能卡包括模数计数器，其通过从智能卡接收符合智能卡协议的外部时钟来生成智能卡的操作时钟读取器，第一次和第二次分频外部时钟以产生第一和第二分频时钟，对第一分频时钟进行A次计数，并对第二分频时钟进行NA次数的计数。

10. 发明申请

US20080079465A1 CLOCK SIGNAL GENERATOR FOR USB DEVICE 有权
标题翻译： USB设备的时钟信号发生器
公开(公告)号：US20080079465A1
公开(公告)日：2008-04-03
申请号：US11775541
申请日：2007-07-10
申请人： Hyuk-Jun Sung , Chan-Yong Kim , Jong-Pil Cho
发明人： Hyuk-Jun Sung , Chan-Yong Kim , Jong-Pil Cho
IPC分类号： H03H11/26 , H03C3/06
CPC分类号： G06F1/04
摘要： A clock signal generator for a USB device. The clock signal generator includes a control circuit and a clock generator that does not need to include a crystal oscillator. The control circuit counts the cycle of the clock signal during the period between two sync signals successively inputted, and generates a frequency control signal corresponding to the count value. The clock generator generates the clock signal with a frequency corresponding to the frequency control signal. The clock signal generator can generate a clock signal that is suitable for the data transfer rate defined, in the USB specification. In addition, the clock; signal generator can generate an RX clock signal so that an RX data signal can be recovered with its energy being stable.
摘要翻译： USB设备的时钟信号发生器。时钟信号发生器包括不需要包括晶振的控制电路和时钟发生器。控制电路在连续输入的两个同步信号之间的周期内对时钟信号的周期进行计数，并产生与计数值对应的频率控制信号。时钟发生器产生具有对应于频率控制信号的频率的时钟信号。时钟信号发生器可以产生适合于在USB规范中定义的数据传输速率的时钟信号。另外，时钟; 信号发生器可以产生RX时钟信号，使得RX数据信号能够以其能量稳定地恢复。

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