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1. 发明授权

US07422943B2 Semiconductor device capacitors with oxide-nitride layers and methods of fabricating such capacitors 有权
标题翻译：具有氧化物氮化物层的半导体器件电容器和制造这种电容器的方法
公开(公告)号：US07422943B2
公开(公告)日：2008-09-09
申请号：US11386660
申请日：2006-03-22
申请人： Jong-cheol Lee , Young-sun Kim , Jung-hee Chung , Jae-hyoung Choi , Se-hoon Oh , Hong-bum Park
发明人： Jong-cheol Lee , Young-sun Kim , Jung-hee Chung , Jae-hyoung Choi , Se-hoon Oh , Hong-bum Park
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/75
摘要： Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer is nitridized.
摘要翻译：提供具有包括下电极，电介质层和包括导电金属氮化物层和掺杂多晶硅锗层的上电极的上电极的电容器。导电金属氮化物层的至少一部分被氧化和/或至少部分介电层被氮化。

2. 发明申请

US20080054400A1 Capacitor and method of manufacturing the same 审中-公开
标题翻译：电容器及其制造方法
公开(公告)号：US20080054400A1
公开(公告)日：2008-03-06
申请号：US11878698
申请日：2007-07-26
申请人： Woo-Sung Lee , Hong-Bum Park , Hyun-Jin Shin , Jong-Bom Seo
发明人： Woo-Sung Lee , Hong-Bum Park , Hyun-Jin Shin , Jong-Bom Seo
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/91 , H01L27/10814 , H01L27/10852
摘要： Example embodiments relate to a capacitor including p-type doped silicon germanium and a method of manufacturing the capacitor. The capacitor may include a lower electrode, a dielectric layer, an upper electrode, a barrier layer and a capping layer. The lower electrode may have a cylindrical shape. The dielectric layer may be on the lower electrode. The dielectric layer may have a uniform thickness. The upper electrode may be on the dielectric layer. The upper electrode may have a more uniform thickness. The capping layer may be on the upper electrode. The capping layer may include a silicon germanium layer doped with p-type impurities. The barrier layer may be between the upper electrode and the capping layer to prevent (or reduce) the p-type impurities from infiltrating into the dielectric layer.
摘要翻译：示例性实施例涉及包括p型掺杂硅锗的电容器和制造电容器的方法。电容器可以包括下电极，电介质层，上电极，阻挡层和封盖层。下部电极可以具有圆筒形状。电介质层可以在下电极上。介电层可以具有均匀的厚度。上电极可以在电介质层上。上部电极可以具有更均匀的厚度。覆盖层可以在上电极上。覆盖层可以包括掺杂有p型杂质的硅锗层。阻挡层可以在上电极和覆盖层之间，以防止（或减少）p型杂质渗透到电介质层中。

3. 发明授权

US07482242B2 Capacitor, method of forming the same, semiconductor device having the capacitor and method of manufacturing the same 有权
标题翻译：电容器，其形成方法，具有电容器的半导体器件及其制造方法
公开(公告)号：US07482242B2
公开(公告)日：2009-01-27
申请号：US11523514
申请日：2006-09-20
申请人： Hong-Bum Park , Woo-Sung Lee , Nam-Kyu Kim , Jung-Hee Chung , Jae-Hyoung Choi
发明人： Hong-Bum Park , Woo-Sung Lee , Nam-Kyu Kim , Jung-Hee Chung , Jae-Hyoung Choi
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Example embodiments relate to a capacitor, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. Other example embodiments are directed to a capacitor having an upper electrode structure including a first upper electrode and a second upper electrode, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. In a method of forming a capacitor, a lower electrode may be formed on a substrate, and then a dielectric layer may be formed on the lower electrode. An upper electrode structure may be formed on the dielectric layer. The upper electrode structure may include a first upper electrode and a second upper electrode. The second upper electrode may include at least two of a silicon layer, a first silicon germanium layer and a second silicon germanium layer doped with p-type impurities. The upper electrode structure may be formed without generating voids between the dielectric layer and the upper electrode structure. The capacitor and the semiconductor device having the upper electrode structure may have improved electrical characteristics.
摘要翻译：示例性实施例涉及电容器，其形成方法，具有电容器的半导体器件及其制造方法。其他示例性实施例涉及具有包括第一上电极和第二上电极的上电极结构的电容器，其形成方法，具有电容器的半导体器件及其制造方法。在形成电容器的方法中，可以在基板上形成下电极，然后在下电极上形成电介质层。上电极结构可以形成在电介质层上。上电极结构可以包括第一上电极和第二上电极。第二上电极可以包括硅层，第一硅锗层和掺杂有p型杂质的第二硅锗层中的至少两个。可以形成上电极结构，而不会在电介质层和上电极结构之间产生空隙。具有上电极结构的电容器和半导体器件可具有改善的电特性。

4. 发明授权

US08298865B2 Method for manufacturing a substrate for a semiconductor package 有权
标题翻译：半导体封装用基板的制造方法
公开(公告)号：US08298865B2
公开(公告)日：2012-10-30
申请号：US13357937
申请日：2012-01-25
申请人： Young Berm Jung , Hong Bum Park , Young Geon Kwon , Seong Kwon Chin , Byeung Ho Kim , Seok Koo Jung
发明人： Young Berm Jung , Hong Bum Park , Young Geon Kwon , Seong Kwon Chin , Byeung Ho Kim , Seok Koo Jung
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/49816 , H01L23/13 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L2224/2919 , H01L2224/32014 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2224/83192 , H01L2224/8385 , H01L2924/01013 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for manufacturing a substrate for a semiconductor package includes the steps of attaching first and second insulation layers which have first surfaces and second surfaces and are formed with conductive layers on the first surfaces, by the medium of a release film which has adhesives attached to both surfaces thereof, such that the second surfaces of the first and second insulation layers face each other; forming first conductive patterns on the first surfaces of the first and second insulation layers by patterning the conductive layers; forming solder masks on the first surfaces of the first and second insulation layers including the first conductive patterns to open portions of the first conductive patterns; and separating the first and second insulation layers from each other by removing the release film.
摘要翻译：一种半导体封装用基板的制造方法，其特征在于，具有将具有第一表面和第二表面的第一绝缘层和第二绝缘层附着在第一表面上的导电层的步骤，使得第一和第二绝缘层的第二表面彼此面对; 通过图案化导电层在第一和第二绝缘层的第一表面上形成第一导电图案; 在包括第一导电图案的第一和第二绝缘层的第一表面上形成焊料掩模以打开第一导电图案的部分; 以及通过除去脱模膜将第一和第二绝缘层彼此分离。

5. 发明申请

US20120118495A1 SUBSTRATE FOR SEMICONDUCTOR PACKAGE, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE HAVING THE SAME 有权
标题翻译：用于半导体封装的基板，其制造方法和具有该半导体封装的半导体封装
公开(公告)号：US20120118495A1
公开(公告)日：2012-05-17
申请号：US13357937
申请日：2012-01-25
申请人： Young Berm JUNG , Hong Bum PARK , Young Geon KWON , Seong Kwon CHIN , Byeung Ho KIM , Seok Koo JUNG
发明人： Young Berm JUNG , Hong Bum PARK , Young Geon KWON , Seong Kwon CHIN , Byeung Ho KIM , Seok Koo JUNG
IPC分类号： B32B38/10
CPC分类号： H01L23/49816 , H01L23/13 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L2224/2919 , H01L2224/32014 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2224/83192 , H01L2224/8385 , H01L2924/01013 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for manufacturing a substrate for a semiconductor package includes the steps of attaching first and second insulation layers which have first surfaces and second surfaces and are formed with conductive layers on the first surfaces, by the medium of a release film which has adhesives attached to both surfaces thereof, such that the second surfaces of the first and second insulation layers face each other; forming first conductive patterns on the first surfaces of the first and second insulation layers by patterning the conductive layers; forming solder masks on the first surfaces of the first and second insulation layers including the first conductive patterns to open portions of the first conductive patterns; and separating the first and second insulation layers from each other by removing the release film.
摘要翻译：一种半导体封装用基板的制造方法，其特征在于，具有将具有第一表面和第二表面的第一绝缘层和第二绝缘层附着在第一表面上的导电层的步骤，使得第一和第二绝缘层的第二表面彼此面对; 通过图案化导电层在第一和第二绝缘层的第一表面上形成第一导电图案; 在包括第一导电图案的第一和第二绝缘层的第一表面上形成焊料掩模以打开第一导电图案的部分; 以及通过除去脱模膜将第一和第二绝缘层彼此分离。

6. 发明申请

US20090294972A1 SUBSTRATE FOR SEMICONDUCTOR PACKAGE, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE HAVING THE SAME 有权
标题翻译：用于半导体封装的基板，其制造方法和具有该半导体封装的半导体封装
公开(公告)号：US20090294972A1
公开(公告)日：2009-12-03
申请号：US12471572
申请日：2009-05-26
申请人： Young Berm JUNG , Hong Bum PARK , Young Geon KWON , Seong Kwon CHIN , Byeung Ho KIM , Seok Koo JUNG
发明人： Young Berm JUNG , Hong Bum PARK , Young Geon KWON , Seong Kwon CHIN , Byeung Ho KIM , Seok Koo JUNG
IPC分类号： H01L23/498 , H01L21/50
CPC分类号： H01L23/49816 , H01L23/13 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L2224/2919 , H01L2224/32014 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2224/83192 , H01L2224/8385 , H01L2924/01013 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for manufacturing a substrate for a semiconductor package includes the steps of attaching first and second insulation layers which have first surfaces and second surfaces and are formed with conductive layers on the first surfaces, by the medium of a release film which has adhesives attached to both surfaces thereof, such that the second surfaces of the first and second insulation layers face each other; forming first conductive patterns on the first surfaces of the first and second insulation layers by patterning the conductive layers; forming solder masks on the first surfaces of the first and second insulation layers including the first conductive patterns to open portions of the first conductive patterns; and separating the first and second insulation layers from each other by removing the release film.
摘要翻译：一种半导体封装用基板的制造方法，其特征在于，具有将具有第一表面和第二表面的第一绝缘层和第二绝缘层附着在第一表面上的导电层的步骤，使得第一和第二绝缘层的第二表面彼此面对; 通过图案化导电层在第一和第二绝缘层的第一表面上形成第一导电图案; 在包括第一导电图案的第一和第二绝缘层的第一表面上形成焊料掩模以打开第一导电图案的部分; 以及通过除去脱模膜将第一和第二绝缘层彼此分离。

7. 发明申请

US20160086943A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20160086943A1
公开(公告)日：2016-03-24
申请号：US14857135
申请日：2015-09-17
申请人： Sun Young LEE , Jae Young Park , Han Ki Lee , Bon Young Koo , Hong Bum Park , Young Su Chung , Jae Jong Han
发明人： Sun Young LEE , Jae Young Park , Han Ki Lee , Bon Young Koo , Hong Bum Park , Young Su Chung , Jae Jong Han
IPC分类号： H01L27/088 , H01L29/423 , H01L29/06
CPC分类号： H01L29/42368 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02238 , H01L21/02247 , H01L21/02252 , H01L21/02255 , H01L21/302 , H01L21/30604 , H01L21/3065 , H01L21/3086 , H01L29/165 , H01L29/66818 , H01L29/7848 , H01L29/7854
摘要： A semiconductor device includes a substrate, an isolation layer on the substrate, and at least one active fin on the substrate. The isolation layer includes a first surface opposite a second surface. The first surface is contiguous with the substrate. The at least one active fin protrudes from the substrate and includes a first region having a side wall above the second surface of the isolation layer and a second region on the first region. The second region has an upper surface. The first region has a first width contiguous with the second surface of the isolation layer and a second width contiguous with the second region. The second width is 60% or greater than the first width (e.g., 60% to 100%).
摘要翻译：半导体器件包括衬底，衬底上的隔离层以及衬底上的至少一个活性鳍。隔离层包括与第二表面相对的第一表面。第一表面与基底相邻。所述至少一个活性翅片从所述基底突出并且包括具有位于所述隔离层的第二表面上方的侧壁的第一区域和所述第一区域上的第二区域。第二区域具有上表面。第一区域具有与隔离层的第二表面邻接的第一宽度和与第二区域相邻的第二宽度。第二宽度为第一宽度（例如，60％至100％）的60％或更大。

8. 发明申请

US20120091469A1 Semiconductor Devices Having Shallow Junctions 审中-公开
标题翻译：具有浅接头的半导体器件
公开(公告)号：US20120091469A1
公开(公告)日：2012-04-19
申请号：US13271615
申请日：2011-10-12
申请人： Keum-Seok Park , Seung-Hun Lee , Byeong-Chan Lee , Sang-Bom Kang , Hong-Bum Park
发明人： Keum-Seok Park , Seung-Hun Lee , Byeong-Chan Lee , Sang-Bom Kang , Hong-Bum Park
IPC分类号： H01L29/772
CPC分类号： H01L29/66621 , H01L29/0847 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer.
摘要翻译：提供了半导体器件，其包括具有从第一表面的相对侧凹入的第一表面和第二表面的衬底，形成在第一表面上并具有栅极绝缘层和栅电极的栅极图案，碳掺杂硅缓冲层形成在第二表面上，以及掺杂有n型掺杂剂或p型掺杂剂的源极和漏极区，其外延生长在硅缓冲层上以从栅极绝缘层的顶表面升高。

9. 发明授权

US08125086B2 Substrate for semiconductor package 有权
标题翻译：半导体封装基板
公开(公告)号：US08125086B2
公开(公告)日：2012-02-28
申请号：US12471572
申请日：2009-05-26
申请人： Young Berm Jung , Hong Bum Park , Young Geon Kwon , Seong Kwon Chin , Byeung Ho Kim , Seok Koo Jung
发明人： Young Berm Jung , Hong Bum Park , Young Geon Kwon , Seong Kwon Chin , Byeung Ho Kim , Seok Koo Jung
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/49816 , H01L23/13 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L2224/2919 , H01L2224/32014 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2224/83192 , H01L2224/8385 , H01L2924/01013 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for manufacturing a substrate for a semiconductor package includes the steps of attaching first and second insulation layers which have first surfaces and second surfaces and are formed with conductive layers on the first surfaces, by the medium of a release film which has adhesives attached to both surfaces thereof, such that the second surfaces of the first and second insulation layers face each other; forming first conductive patterns on the first surfaces of the first and second insulation layers by patterning the conductive layers; forming solder masks on the first surfaces of the first and second insulation layers including the first conductive patterns to open portions of the first conductive patterns; and separating the first and second insulation layers from each other by removing the release film.
摘要翻译：一种半导体封装用基板的制造方法，其特征在于，具有将具有第一表面和第二表面的第一绝缘层和第二绝缘层附着在第一表面上的导电层的步骤，使得第一和第二绝缘层的第二表面彼此面对; 通过图案化导电层在第一和第二绝缘层的第一表面上形成第一导电图案; 在包括第一导电图案的第一和第二绝缘层的第一表面上形成焊料掩模以打开第一导电图案的部分; 以及通过除去脱模膜将第一和第二绝缘层彼此分离。

10. 发明申请

US20110275197A1 SEMICONDUCTOR MEMORY DEVICE, METHOD OF FORMING THE SAME, AND MEMORY SYSTEM 审中-公开
标题翻译：半导体存储器件，其形成方法和存储器系统
公开(公告)号：US20110275197A1
公开(公告)日：2011-11-10
申请号：US13100680
申请日：2011-05-04
申请人： Hong-bum PARK , Dae-Han Yoo , Eun-Young Lee , Yongwoo Hyung , Youngsub You , Jinkwon Bok
发明人： Hong-bum PARK , Dae-Han Yoo , Eun-Young Lee , Yongwoo Hyung , Youngsub You , Jinkwon Bok
IPC分类号： H01L21/20
CPC分类号： H01L27/11578 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L27/10852 , H01L27/11582 , H01L28/91 , H01L29/66833 , H01L29/7926
摘要： A method of forming a semiconductor memory device, a semiconductor memory device, and a memory system, the method including forming a thin film structure on a semiconductor substrate such that the thin film structure includes a plurality of thin films; patterning the thin film structure to form a through region in the thin film structure; forming a first silicon film using a first precursor such that the first silicon film covers the through region; and forming a second silicon film on the first silicon film using a second precursor, wherein the first precursor is different from the second precursor.
摘要翻译：一种形成半导体存储器件，半导体存储器件和存储器系统的方法，所述方法包括在半导体衬底上形成薄膜结构，使得薄膜结构包括多个薄膜; 图案化薄膜结构以在薄膜结构中形成贯穿区域; 使用第一前体形成第一硅膜，使得第一硅膜覆盖通孔区域; 以及使用第二前体在所述第一硅膜上形成第二硅膜，其中所述第一前体与所述第二前体不同。

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