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1. 发明授权

US08484448B2 Information processing device 有权
标题翻译：信息处理装置
公开(公告)号：US08484448B2
公开(公告)日：2013-07-09
申请号：US13399023
申请日：2012-02-17
申请人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
发明人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
IPC分类号： G06F9/00 , G06F15/177
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.
摘要翻译：信息处理系统，包括具有低于第一操作电流的第一操作模式和第二操作模式，当引导地址寄存器从第二操作模式返回到第一操作模式时，首先保存由处理单元执行的指令的地址的寄存器，其中该地址为当第二至第一操作模式转换时，输出到处理单元，其中引导地址寄存器是可重写的，信息保持电路保持外围电路模块寄存器的值，其中信息保持电路在第二操作模式中保持关于外围电路模块寄存器，并且将关于第二至第一操作模式移位的信息保持电路中保存的信息传送到外围电路模块寄存器，并且其中当在第二操作模式中从系统外部发布中断请求时信息处理系统执行与内部相对应的中断处理破产请求

2. 发明申请

US20120151197A1 INFORMATION PROCESSING DEVICE 有权
标题翻译：信息处理设备
公开(公告)号：US20120151197A1
公开(公告)日：2012-06-14
申请号：US13399023
申请日：2012-02-17
申请人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
发明人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
IPC分类号： G06F9/00
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.
摘要翻译：信息处理系统，包括具有低于第一操作电流的第一操作模式和第二操作模式，当引导地址寄存器从第二操作模式返回到第一操作模式时，首先保存由处理单元执行的指令的地址的寄存器，其中该地址为当第二至第一操作模式转换时，输出到处理单元，其中引导地址寄存器是可重写的，信息保持电路保持外围电路模块寄存器的值，其中信息保持电路在第二操作模式中保持关于外围电路模块寄存器，并且将关于第二至第一操作模式移位的信息保持电路中保存的信息传送到外围电路模块寄存器，并且其中当在第二操作模式中从系统外部发布中断请求时信息处理系统执行与内部相对应的中断处理破产请求

3. 发明授权

US07380149B2 Information processing device 有权
标题翻译：信息处理装置
公开(公告)号：US07380149B2
公开(公告)日：2008-05-27
申请号：US10849063
申请日：2004-05-20
申请人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
发明人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
IPC分类号： G06F1/26 , G06F1/24 , G06F1/32 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： A mechanism of making a low standby current caused by power off compatible with a fast return operation from a standby caused by an interrupt is realized. An information processing device has a first area that includes a central processing unit and peripheral circuit modules, a second area having information holding circuits for holding values of registers contained in the peripheral circuit modules, and a first power switch for controlling supply of a current to the first area. When the information processing device operates in a first mode, an operating current is supplied to the first area and the second area. When the information processing device operates in a second mode, the first power switch is controlled so that the supply of the current to the first area can be shut off, and the supply of the current to the second area is continued.
摘要翻译：实现了由与中断引起的来自待机的快速返回操作兼容的断电引起的低待机电流的机制。信息处理装置具有包括中央处理单元和外围电路模块的第一区域，具有用于保持包含在外围电路模块中的寄存器的值的信息保持电路的第二区域和用于控制向外部电路提供电流的第一电源开关第一个区域。当信息处理装置以第一模式操作时，工作电流被提供给第一区域和第二区域。当信息处理装置在第二模式下操作时，控制第一电源开关，使得可以切断对第一区域的电流的供应，并且继续向第二区域供应电流。

4. 发明授权

US08122233B2 Information processing device 有权
标题翻译：信息处理装置
公开(公告)号：US08122233B2
公开(公告)日：2012-02-21
申请号：US12124232
申请日：2008-05-21
申请人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
发明人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
IPC分类号： G06F9/00 , G06F15/177
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： An information processing device, including: a processing unit; a peripheral circuit module; and a boot address register, wherein the information processing device comprises a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode, wherein the boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein the address is output from said boot address to the processing unit when said information processing device shifts from said second operation mode to said first operation mode.
摘要翻译：一种信息处理装置，包括：处理单元; 外围电路模块; 以及引导地址寄存器，其中所述信息处理设备包括具有低于所述第一操作模式的操作电流的第一操作模式和第二操作模式，其中所述引导地址寄存器保存要执行的指令的地址所述处理单元首先当所述引导地址寄存器从所述第二操作模式返回到所述第一操作模式时，其中当所述信息处理设备从所述第二操作模式转换到所述第一操作时，所述地址从所述引导地址输出到所述处理单元模式。

5. 发明申请

US20080282076A1 INFORMATION PROCESSING DEVICE 有权
标题翻译：信息处理设备
公开(公告)号：US20080282076A1
公开(公告)日：2008-11-13
申请号：US12124232
申请日：2008-05-21
申请人： Motokazu OZAWA , Naohiko IRIE , Saneaki TAMAKI , Hisayoshi IDE , Miki HAYAKAWA
发明人： Motokazu OZAWA , Naohiko IRIE , Saneaki TAMAKI , Hisayoshi IDE , Miki HAYAKAWA
IPC分类号： G06F1/24
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： Abstract An information processing device, including: a processing unit; a peripheral circuit module; and a boot address register, wherein the information processing device comprises a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode, wherein the boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein the address is output from said boot address to the processing unit when said information processing device shifts from said second operation mode to said first operation mode.
摘要翻译：一种信息处理装置，包括：处理单元; 外围电路模块; 以及引导地址寄存器，其中所述信息处理设备包括具有低于所述第一操作模式的操作电流的第一操作模式和第二操作模式，其中所述引导地址寄存器保存要执行的指令的地址所述处理单元首先当所述引导地址寄存器从所述第二操作模式返回到所述第一操作模式时，其中当所述信息处理设备从所述第二操作模式转换到所述第一操作时，所述地址从所述引导地址输出到所述处理单元模式。

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