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    • 3. 发明授权
    • System and method for processing series of processes in given order having processing status generation with tables storing status including beginning, end and existence segment
    • 用于以给定顺序处理一系列处理的系统和方法,其具有处理状态生成,其中存储状态包括开始,结束和存在段
    • US08209693B2
    • 2012-06-26
    • US12039412
    • 2008-02-28
    • Hisato Matsuo
    • Hisato Matsuo
    • G06F9/46
    • G06F3/0656G06F3/0613G06F3/0682
    • Provided is a technology capable of managing the processing status of hardware blocks by a less number of registers. A processing system includes a buffer composed of a plurality of segments which store data, which is to be input to the processing system, in transactions in the order of inputting, respectively; a plurality of processing units which perform a series of processes in a given order for the data; a plurality of first tables corresponding to the plurality of processing units, respectively, the first tables each storing beginning information which indicates a beginning segment among a plurality of segments at continuous addresses completed in the process by the corresponding processing unit, end information which indicates an end segment among them, and existence information which indicates the presence or absence of segments completed in the process by the corresponding processing unit; and a management unit which manages a data transfer between the buffer and the plurality of processing units so that the series of processes are performed in a given order on the basis of the processing status of the series of processes retained in the plurality of first tables.
    • 提供了能够通过较少数量的寄存器来管理硬件块的处理状态的技术。 一种处理系统,包括分别以输入顺序存储要输入到处理系统的数据的多个段的缓冲器; 多个处理单元,以给定顺序执行数据的一系列处理; 分别对应于多个处理单元的多个第一表,每个存储开始信息的第一表,其中表示在相应处理单元处理完成的连续地址的多个段中的起始段,表示一个 以及存在信息,其指示由对应的处理单元在该处理中完成的段的存在或不存在; 以及管理单元,其管理所述缓冲器和所述多个处理单元之间的数据传送,使得根据保持在所述多个第一表中的所述一系列处理的处理状态,以给定的顺序执行所述一系列处理。
    • 4. 发明申请
    • Arbitrated Access To Memory Shared By A Processor And A Data Flow
    • 由处理器和数据流共享的内存的仲裁访问
    • US20110125946A1
    • 2011-05-26
    • US12916668
    • 2010-11-01
    • Masayuki DemuraHisato MatsuoKeisuke Tanaka
    • Masayuki DemuraHisato MatsuoKeisuke Tanaka
    • G06F13/18G06F12/06
    • G06F13/161G06F13/1673Y02D10/14
    • Memory access arbitration allowing a shared memory to be used both as a memory for a processor and as a buffer for data flows, including an arbiter unit that makes assignment for access requests to the memory sequentially and transfers blocks of data in one round-robin cycle according to bandwidths required for the data transfers, sets priorities for the transfer blocks so that the bandwidths required for the data transfers are met by alternate transfer of the transfer blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined transfer length exerts less effect on bandwidths for data flow transfers in predetermined intervals between the transfer blocks.
    • 存储器访问仲裁允许共享存储器既用作处理器的存储器又用作数据流的缓冲器,包括仲裁器单元,其顺序地对存储器的访问请求进行分配,并在一个循环周期中传送数据块 根据数据传输所需的带宽,设置传输块的优先级,使得通过传输块的交替传送来满足数据传输所需的带宽,并且执行对处理器的访问,其具有为 在一个循环周期中从处理器到存储器的访问时间,使得来自具有最高优先级并且具有预定传送长度的处理器的访问对传输块之间的预定间隔中的数据流传输的带宽的影响较小。
    • 8. 发明申请
    • MEMORY ACCESS DEVICE FOR MEMORY SHARING AMONG PLURALITY OF PROCESSORS, AND ACCESS METHOD FOR SAME
    • 用于处理器多重存储器共享的存储器访问设备及其访问方法
    • US20140059286A1
    • 2014-02-27
    • US13989743
    • 2011-10-06
    • Hisato MatsuoRika NagaharaKenji Ohtani
    • Hisato MatsuoRika NagaharaKenji Ohtani
    • G06F13/16
    • G11C7/1048G06F13/1642G06F13/1647G06F13/1663G06F13/4234G11C7/1072
    • Provided is a memory access device for a shared memory mechanism of main memory for a plurality of CPUs. The present invention includes a plurality of CPUs using memory as main memory, another function block using memory as a buffer, a CPU interface which controls access transfer from the plurality of CPUs to memory, and a DRAM controller for performing arbitration of the access transfer to the memory. Therein, the CPU interface causes access requests from the plurality of CPUs to wait, and receives and stores the address, data transfer mode and data size of each access, notifies the DRAM controller of the access requests, and then, upon receiving grant signals for the access requests, sends information to the DRAM controller according to the grant signals, whereupon the DRAM controller receives the grant signals, and on the basis of the access arbitration, specifies CPUs for which transfers have been granted so as to send the grant signals to the CPU interface.
    • 提供了一种用于多个CPU的主存储器的共享存储器机构的存储器访问装置。 本发明包括使用存储器作为主存储器的多个CPU,使用存储器作为缓冲器的另一功能块,控制从多个CPU到存储器的访问传输的CPU接口,以及用于执行访问转移的仲裁的DRAM控制器 记忆。 其中,CPU接口使得来自多个CPU的访问请求等待,并且接收并存储每个访问的地址,数据传输模式和数据大小,向DRAM控制器通知访问请求,然后在接收到 访问请求根据授权信号向DRAM控制器发送信息,于是DRAM控制器接收授权信号,并且基于访问仲裁,指定已经被授权传输的CPU,以便将授权信号发送到 CPU接口。