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    • 10. 发明授权
    • Parallel accessible memory device
    • 并行可访问存储设备
    • US5008852A
    • 1991-04-16
    • US175484
    • 1988-03-30
    • Hiroshi Mizoguchi
    • Hiroshi Mizoguchi
    • G06F12/00G06F12/02G06F12/06G06T1/60
    • G06T1/60G06F12/0207
    • A parallel-accessible memory device of one or multiple dimensions has submemories for the respective dimensions. Each of the submemories has a capacity provided by dividing the total memory capacity by positive integers given for the respective dimensions. The memory device comprises an address converting section for generating addresses of the submemories of the respective dimensions according to dimensional addresses; a data rearranging section for rearranging input and output data of the submemories in a required order, the input and output data being specified by the submemory addresses from the address converting section; and a write controlling section for selectively renewing data in a region of the submemories of the respective dimensions.
    • 一个或多个维度的并行可访问存储器件具有用于各个维度的子存储器。 每个子存储器具有通过将总存储器容量除以给定的相应尺寸的正整数而提供的容量。 存储装置包括:地址转换部分,用于根据维度地址产生相应尺寸的子存储器的地址; 数据重排部分,用于以所需的顺序重新排列所述子系统的输入和输出数据,所述输入和输出数据由所述地址转换部分的子存储器地址指定; 以及写控制部分,用于选择性地更新相应尺寸的子存储器区域中的数据。