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1. 发明授权

US06480542B1 Method for decoding compressed video data with a reduced memory requirement 失效
标题翻译：用于以减少的存储器要求对压缩视频数据进行解码的方法
公开(公告)号：US06480542B1
公开(公告)日：2002-11-12
申请号：US08793356
申请日：1997-02-21
申请人： Stefan Prange , Heribert Geib , Bernard Hammer , Jürgen Pandel
发明人： Stefan Prange , Heribert Geib , Bernard Hammer , Jürgen Pandel
IPC分类号： H04N718
CPC分类号： H04N19/577 , H04N19/423 , H04N19/426 , H04N19/61
摘要： For the purpose of bidirectional movement-compensated interpolation, it is proposed, when decoding compressed video sequences, completely to decode only one of the two reference frames. Only those respective picture areas of the other reference frame are decompressed which overlap with the picture area to be determined of the interpolated frame, taking account of a displacement corresponding to the movement compensation. As a result, a considerable reduction in the memory requirement of the decoding hardware is possible.
摘要翻译：为了双向运动补偿插值的目的，提出了在解码压缩视频序列时完全解码两个参考帧中的一个。考虑到与移动补偿相对应的位移，仅解压缩与要被确定的内插帧的图像区域重叠的另一个参考帧的各个图像区域。结果，可以大大减少解码硬件的存储器需求。

2. 发明授权

US06353639B1 Filter configuration and slope detector for quadrature amplitude modulated signals 失效
标题翻译：用于正交幅度调制信号的滤波器配置和斜率检测器
公开(公告)号：US06353639B1
公开(公告)日：2002-03-05
申请号：US09531193
申请日：2000-03-20
申请人： Stefan Prange , Heribert Geib , Erik De Man
发明人： Stefan Prange , Heribert Geib , Erik De Man
IPC分类号： H04L512
CPC分类号： H04L27/3854 , H03D1/2245 , H03D3/007 , H04N5/205 , H04N5/455
摘要： A filter configuration for a demodulated QAM signal has a first channel for a cosine demodulated component of the QAM signal, a second channel for a sine demodulated component of the QAM signal, a filter circuit, which receives the two signal components and for each signal component has one transfer function that is composed of terms in phase with this signal component and terms phase-shifted from it by &pgr;/2 and/or −&pgr;/2. The circuit configuration also includes a cross branch for picking up signal portions from the respectively other channel that correspond to the phase-shifted terms of the transfer function. In a first state, the circuit configuration connects the input of the cross branch to the first channel and the output of the cross branch to the second channel, and in a second state connects the input of the cross branch to the second channel and the output of the cross branch to the first channel. A slope detector especially suitable for use with this filter configuration is also provided. The circuit configuration requires a reduced amount of circuitry and can be integrated on a small surface area of a semiconductor substrate.
摘要翻译：用于解调的QAM信号的滤波器配置具有用于QAM信号的余弦解调分量的第一信道，用于QAM信号的正弦解调分量的第二信道，接收两个信号分量的滤波器电路，以及用于每个信号分量具有一个传递函数，其由该信号分量的相位项和由π/ 2和/或-pi / 2相移的项组成。电路配置还包括用于从与传输函数的相移项对应的相应的其它信道中拾取信号部分的交叉分支。在第一状态下，电路配置将交叉分支的输入端与第一通道和交叉分支的输出连接到第二通道，并且在第二状态下将交叉分支的输入连接到第二通道，输出的交叉分支到第一个通道。还提供了特别适用于该过滤器配置的斜率检测器。电路配置需要减少电路量，并且可以集成在半导体衬底的小表面区域上。

3. 发明授权

US5751357A Method and arrangement for coding and decoding a video data stream for all picture elements of the video data stream 失效
标题翻译：用于对视频数据流的所有图像元素的视频数据流进行编码和解码的方法和装置
公开(公告)号：US5751357A
公开(公告)日：1998-05-12
申请号：US677041
申请日：1996-07-08
申请人： Heribert Geib
发明人： Heribert Geib
IPC分类号： H04N5/92 , G06T9/00 , H03M7/30 , H04N1/41 , H04N19/126 , H04N19/61 , H04N7/50
CPC分类号： H04N19/126 , H04N19/61 , H04N19/124
摘要： A run length coding (RLC) is implemented in a coder/decoder unit (CD) in a forward path (VP) and a run length decoding (RLD) is implemented at the beginning of reconstruction in a reconstruction path for an internal reconstruction of the video data stream. As a result an added outlay seems to occur as compared to known methods. However, an interleaving of tasks that were successively implemented in previous methods is thereby enabled. A substantial reduction of the overall outlay compared to known procedures is achieved by the interleaving of the scan method (SV), quantizing (Q) and run length coding (RLC), run length decoding (RLD), inverse quantizing (IQ) and the inverse scan method (ISV).
摘要翻译：在前向路径（VP）中的编码器/解码器单元（CD）中实现游程长度编码（RLC），并且在重建路径中的重建路径中实现游程长度解码（RLD），用于内部重建视频数据流。因此，与已知方法相比，似乎发生了额外的费用。然而，由此启用在先前方法中连续实现的任务的交错。通过扫描方法（SV），量化（Q）和游程长度编码（RLC），游程长度解码（RLD），反向量化（IQ）和逆量化（Q）的交织来实现与已知程序相比的整体支出的实质性减少逆扫描法（ISV）。

4. 发明授权

US5448194A Circuit for the buffer storage of a bit, and use of the circuit as an address buffer store 失效
标题翻译：电路用于缓冲存储一位，并将电路用作地址缓冲存储
公开(公告)号：US5448194A
公开(公告)日：1995-09-05
申请号：US290801
申请日：1994-08-17
申请人： Heribert Geib
发明人： Heribert Geib
IPC分类号： G11C11/408 , G11C11/413 , H03K3/356
CPC分类号： G11C11/4082
摘要： A storage element is provided in a circuit arrangement for latching one bit. A first MOS transistor (T1) is provided which, when a first control signal (S1) is present, switches an input signal corresponding to the bit to the input of the storage element. The storage element is provided with circuit elements by which an output signal at the output of the storage element is brought to a predetermined potential in dependence on the level of the input signal. The circuit arrangement is particularly suitable for constructing an address latch for DRAMs, particularly of the 16-M generation.
摘要翻译：存储元件设置在用于锁存一位的电路装置中。提供了第一MOS晶体管（T1），当存在第一控制信号（S1）时，将与位相对应的输入信号切换到存储元件的输入。存储元件设置有电路元件，通过该电路元件，存储元件的输出端的输出信号根据输入信号的电平达到预定电位。该电路布置特别适用于构建用于DRAM的地址锁存器，特别是16M代的地址锁存器。

5. 发明授权

US07030434B1 Arrangement with image sensors 有权
标题翻译：图像传感器布置
公开(公告)号：US07030434B1
公开(公告)日：2006-04-18
申请号：US10089570
申请日：2000-09-28
申请人： Wolfgang Krautschneider , Heribert Geib , Franz Hofmann , Till Schlösser
发明人： Wolfgang Krautschneider , Heribert Geib , Franz Hofmann , Till Schlösser
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14609
摘要： A memory transistor and a selection transistor of an image sensor are connected in series and between a bit line (B5) and a reference line (R5). A gate electrode of the selection transistor is connected to a word line (W5), which extends crosswise in relation to the bit line (B5). A diode of the image sensor is switched between a gate electrode (G5) of the memory transistor and a first source/drain area (S/D5) of the memory transistor, which is connected to the selection transistor in such a way is polarized towards the first source/drain area (S/D5) of the memory transistor and in the reverse direction. A photodiode of the image sensor is switched between a voltage connection and either the gate electrode (G5) of the memory transistor or the first source/drain area (S/D5) of the memory transistor in such a way that it is polarized towards the voltage connection and in the reverse direction.
摘要翻译：图像传感器的存储晶体管和选择晶体管串联连接在位线（B 5）和基准线（R 5）之间。选择晶体管的栅电极连接到相对于位线（B 5）横向延伸的字线（W 5）。图像传感器的二极管在存储晶体管的栅电极（G 5）和存储晶体管的第一源极/漏极区域（S / D 5）之间切换，以这样的方式连接到选择晶体管朝向存储晶体管的第一源极/漏极区域（S / D 5）偏振并且沿相反方向偏振。图像传感器的光电二极管在存储晶体管的栅电极（G 5）或存储晶体管的第一源/漏区（S / D 5）的电压连接和栅极之间切换，使得其被极化朝向电压连接和相反方向。

6. 发明授权

US06831686B1 Method and device for the exposure-dependent noise correction in image sensors which can be addressed in lines and columns 失效
标题翻译：用于图像传感器中曝光相关噪声校正的方法和装置，可以在行和列中进行寻址
公开(公告)号：US06831686B1
公开(公告)日：2004-12-14
申请号：US09806633
申请日：2001-03-30
申请人： Ivo Koren , Heribert Geib , Ulrich Ramacher
发明人： Ivo Koren , Heribert Geib , Ulrich Ramacher
IPC分类号： H04M964
CPC分类号： H04N5/365 , H04N5/2176 , H04N5/3575 , H04N5/361
摘要： Method and device for the exposure-dependent noise correction in images sensor which can be addressed in lines and columns are converted into digital values and an offset voltage correction is carried out by a summer, a gain correction is carried out by a multiplier, and an exposure-dependent dark current correction is carried out by a further summer. Further, the coefficients that depend on the line number, the column number and the integration time, are determined by linear approximations. As a result, the fixed pattern noise (PFN) in CMOS image sensor can be efficiently suppressed with a relatively low outlay.
摘要翻译：图像传感器中的曝光相关噪声校正的方法和装置可以在行和列中被寻址，被转换为数字值，并且通过加法器执行偏移电压校正，增益校正由乘法器执行，并且暴露依赖的暗电流校正是在夏天进行的。此外，取决于行号，列号和积分时间的系数由线性近似来确定。结果，CMOS图像传感器中的固定图案噪声（PFN）可以以相对较低的成本被有效地抑制。

7. 发明授权

US06278734B1 Process for decoding and coding a compressed video data stream with reduced memory requirements 失效
标题翻译：具有减少的存储器要求对压缩视频数据流进行解码和编码的过程
公开(公告)号：US06278734B1
公开(公告)日：2001-08-21
申请号：US08981267
申请日：1997-12-22
申请人： Heribert Geib , Stefan Prange
发明人： Heribert Geib , Stefan Prange
IPC分类号： H04B166
CPC分类号： H04N19/577 , H04N19/423 , H04N19/428 , H04N19/61
摘要： The method is for coding and for decoding a video data stream, only one picture which is required for the reconstruction of interpolated pictures being stored in completely decompressed form during the coding or during the decoding of the video data stream. That part of a second basic picture (G2) which is required in decompressed form for the construction or reconstruction of an interpolated picture is temporarily decompressed in each case. A further possibility envisages storing a first basic picture (G1) and the second basic picture (G2) in compressed form and in each case temporarily decompressing only those regions which are required for the construction or reconstruction of an interpolated picture.
摘要翻译：该方法用于对视频数据流进行编码和解码，在编码期间或在视频数据流的解码期间，只有一个完全解压缩形式的内插图像重建所需的图像。在每种情况下，暂时解压缩内插图像的构造或重建的解压缩形式所需的第二基本图像（G2）的部分。另外的可能性是设想以压缩形式存储第一基本图像（G1）和第二基本图像（G2），并且在每种情况下仅暂时解压缩内插图像的构造或重构所需的那些区域。

8. 发明授权

US5333121A Dynamic semiconductor memory having local read amplifier driver circuits which are optimized with respect to their drive function 失效
标题翻译：动态半导体存储器具有相对于它们的驱动功能优化的本地读取放大器驱动器电路
公开(公告)号：US5333121A
公开(公告)日：1994-07-26
申请号：US984579
申请日：1993-03-09
申请人： Heribert Geib
发明人： Heribert Geib
IPC分类号： G11C11/401 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C7/00
CPC分类号： G11C11/4097 , G11C11/4091
摘要： The dynamic semiconductor memory which has at least one block of memory (WLB), in which s block of memory has in each case a plurality of bit line blocks (TB, TB' . . . ) which has for each bit line block a local SAN driver (LTN), and possibly also a local SAP driver (LTP) for driving the read amplifiers (LV) belonging to this bit line block (TB), in order to avoid interfering voltage drops on long driver lines, and which has, to achieve an optimized drive function, multi-stage local SAN drivers (LTN) or SAP drivers (LTP) whose transistors generally have different channel widths.
摘要翻译： PCT No.PCT / DE91 / 00695 Sec。 371日期1993年3月9日 102（e）1993年3月9日PCT 1991年9月2日PCT PCT。第WO92 / 05557号公报日期：1992年4月2日。具有至少一个存储器块（WLB）的动态半导体存储器，其中存储器块在每种情况下都具有多个位线块（TB，TB'...）对于每个位线块，本地SAN驱动器（LTN）以及可能还有用于驱动属于该位线块（TB）的读取放大器（LV）的本地SAP驱动器（LTP），以避免长时间干扰电压降驱动器线路，并且其具有实现优化的驱动功能的多级本地SAN驱动器（LTN）或其驱动器（LTP），其晶体管通常具有不同的通道宽度。

9. 发明授权

US5293343A Dynamic semiconductor memory having a read amplifier drive circuit for achieving short access times with a low total peak current 失效
标题翻译：具有读取放大器驱动电路的动态半导体存储器，用于以较低的总峰值电流实现短的存取时间
公开(公告)号：US5293343A
公开(公告)日：1994-03-08
申请号：US988956
申请日：1993-03-10
申请人： Wolfgang Raab , Heribert Geib
发明人： Wolfgang Raab , Heribert Geib
IPC分类号： G11C11/401 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C7/00
CPC分类号： G11C11/4091 , G11C11/4097
摘要： The dynamic semiconductor memory is divided into word line blocks and bit line blocks, word line blocks consisting of a plurality of bit line blocks, which includes for each bit line block a local SAN driver (LTN) and an decelerator circuit for driving the read amplifiers (LV1 . . . LVi) associated with the respective bit line block, and the accelerator circuits of which can be driven in such a way that, to achieve a low total peak current, only the accelerator circuit belonging to the bit line block is active whose bit lines are switched through to IO lines (IO, ION). The accelerator circuit consists, for example, of only one driver transistor (NT.sub.n+1) in each case.
摘要翻译： PCT No.PCT / DE91 / 00697 Sec。 371日期1993年3月10日 102（e）1993年3月10日PCT 1991年9月3日PCT PCT。公开号WO92 / 05558 日期：1992年4月2日。动态半导体存储器分为字线块和位线块，由多个位线块组成的字线块，其包括对于每个位线块，本地SAN驱动器（LTN）和减速电路，用于驱动与相应位线块相关联的读取放大器（LV1 ... LVi），并且其加速器电路可以以这样的方式被驱动：为了实现低总峰值电流，仅仅加速器电路属于位线块被激活，其位线被切换到IO线（IO，ION）。在每种情况下，加速器电路例如仅由一个驱动晶体管（NTn + 1）构成。

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