专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6107852A Method and device for the reduction of latch insertion delay 失效
标题翻译：用于减少锁存器插入延迟的方法和装置
公开(公告)号：US6107852A
公开(公告)日：2000-08-22
申请号：US81001
申请日：1998-05-19
申请人： Christopher McCall Durham , Michael Ju Hyeok Lee , Visweswara Rao Kodali , Harsh Dev Sharma
发明人： Christopher McCall Durham , Michael Ju Hyeok Lee , Visweswara Rao Kodali , Harsh Dev Sharma
IPC分类号： H03K3/012 , H03K3/356
CPC分类号： H03K3/012 , H03K3/356156
摘要： A method and device are disclosed for the reduction of the penalty associated with inserting a latch in a circuit which is utilized to implement an integrated circuit in a data-processing system. A semiconductor device is disclosed which includes a main latch circuit, a feedback latch circuit and an output terminal. The main latch circuit is capable of receiving an input data signal and an input clock signal. The main latch circuit generates a latch output signal in response to the input data and clock signals. The feedback latch circuit is capable of receiving the latch output signal from the main latch circuit and storing the latch output signal. The feedback latch circuit is capable of generating a feedback latch circuit output signal which is received by the main latch circuit to maintain the latch output signal. The output terminal of the device is coupled to the feedback latch circuit for outputting a device output signal which is equal to the feedback latch circuit output signal.
摘要翻译：公开了一种用于减少与用于在数据处理系统中实现集成电路的电路中插入锁存相关联的惩罚的方法和装置。公开了一种半导体器件，其包括主锁存电路，反馈锁存电路和输出端子。主锁存电路能够接收输入数据信号和输入时钟信号。主锁存电路根据输入数据和时钟信号产生锁存输出信号。反馈锁存电路能够接收来自主锁存电路的锁存输出信号并存储锁存器输出信号。反馈锁存电路能够产生由主锁存电路接收的反馈锁存电路输出信号，以维持锁存输出信号。设备的输出端耦合到反馈锁存电路，用于输出等于反馈锁存电路输出信号的器件输出信号。

2. 发明授权

US07886238B1 Visual yield analysis of intergrated circuit layouts 有权
标题翻译：集成电路布局的视觉产量分析
公开(公告)号：US07886238B1
公开(公告)日：2011-02-08
申请号：US11564223
申请日：2006-11-28
申请人： Harsh Dev Sharma , Rajeev Srivastava , Srinivas R. Kommoori , Bharat Bhushan , Mithunjoy Parui , Albert Lee
发明人： Harsh Dev Sharma , Rajeev Srivastava , Srinivas R. Kommoori , Bharat Bhushan , Mithunjoy Parui , Albert Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net segments in the wire interconnect together. The method further includes performing a yield analysis of the net segments in the integrated circuit layout and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect yield scores of the net segments in the integrated circuit layout.
摘要翻译：公开了基于产量分析优化布局的系统和方法。该方法包括生成具有两层或更多层导线互连的集成电路布局，以形成网段，并且具有一个或多个通孔接触层以将导线互连中的网段耦合在一起。该方法还包括对集成电路布局中的网段执行收益率分析，并使用多个不透明度级别对收益率分析的视觉描绘来显示净段以反映集成电路布局中的网段的收益率。

3. 发明授权

US07600208B1 Automatic placement of decoupling capacitors 失效
标题翻译：自动放置去耦电容
公开(公告)号：US07600208B1
公开(公告)日：2009-10-06
申请号：US11669872
申请日：2007-01-31
申请人： Harsh Dev Sharma , Rajeev Srivastava , Srivinas R. Kommoori , Bharat Bhushan , Mithunjoy Parui , Albert Lee
发明人： Harsh Dev Sharma , Rajeev Srivastava , Srivinas R. Kommoori , Bharat Bhushan , Mithunjoy Parui , Albert Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5068
摘要： Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In one embodiment of the invention, the method includes generating one or more regions of the integrated circuit design, with each region having one or more cells, determining an amount of decoupling capacitance required in each region of the integrated circuit design by analyzing each cell in the region, and adding sufficient decoupling capacitor cells to the region to compensate for the potential voltage drop.
摘要翻译：公开了用于在集成电路中自动放置去耦电容器以补偿电网中可能出现的电压降的方法，系统和装置。在本发明的一个实施例中，该方法包括生成集成电路设计的一个或多个区域，每个区域具有一个或多个单元，通过分析集成电路设计的每个单元来确定集成电路设计的每个区域中所需的去耦电容量并且向该区域添加足够的去耦电容器单元以补偿潜在的电压降。

4. 发明授权

US07810063B1 Graphical user interface for prototyping early instance density 有权
标题翻译：用于原型设计早期密度的图形用户界面
公开(公告)号：US07810063B1
公开(公告)日：2010-10-05
申请号：US11670366
申请日：2007-02-01
申请人： Harsh Dev Sharma , Po-chiang Albert Lee , Rajeev Srivastava , Srinivas R. Kommoori , Bharat Bhushan , Mithunjoy Parui
发明人： Harsh Dev Sharma , Po-chiang Albert Lee , Rajeev Srivastava , Srinivas R. Kommoori , Bharat Bhushan , Mithunjoy Parui
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/74
摘要： According to various embodiments of the invention electronic circuit design information can be presented to a designer by determining an electronic circuit comprising at least two gates and by determining a distance of one gate relative to another gate in a stage. A visual indicator for the stage can be calculated based on the distances between at least two gates in the stage. The visual indicator can then be displayed. The visual indicator can be a color and the relative distance can be indicated by brightness, hue or saturation, etc. Alternatively, the visual indicator can be a pattern and the relative distance between at least two gates can be indicated by darkness of the pattern.
摘要翻译：根据本发明的各种实施例，电子电路设计信息可以通过确定包括至少两个门的电子电路并且通过在一个阶段中确定一个门相对于另一个门的距离来呈现给设计者。可以基于舞台中至少两个门之间的距离来计算舞台的视觉指示器。然后可以显示视觉指示器。视觉指示器可以是一种颜色，并且相对距离可以由亮度，色相或饱和度等指示。或者，视觉指示器可以是图案，并且可以通过图案的黑暗来指示至少两个门之间的相对距离。

5. 发明授权

US06208907B1 Domino to static circuit technique 失效
标题翻译： Domino到静态电路技术
公开(公告)号：US06208907B1
公开(公告)日：2001-03-27
申请号：US09016653
申请日：1998-01-30
申请人： Christopher McCall Durham , Visweswara Rao Kodali , Douglas Ele Martin , Harsh Dev Sharma
发明人： Christopher McCall Durham , Visweswara Rao Kodali , Douglas Ele Martin , Harsh Dev Sharma
IPC分类号： G06F1900
CPC分类号： G06F9/38 , H03K19/0963 , H03K19/1735
摘要： A method and apparatus is provided for enabling the transformation of a domino circuit to a static circuit without requiring the re-design of the chip or integrated circuit mask set. The domino circuit masks may be designed to include additional unconnected devices as appropriate which may be added or connected into the circuit after chip design release by changing only interconnection masks. Spare devices can be added and selectively used to make a domino circuit metal-mask programmable into a logically equivalent static circuit. In a first exemplary method, extra devices are added to, and/or existing devices are re-wired in the domino circuitry to make a complementary equivalent static gate. In a second exemplary methodology, the domino circuit is converted into a pseudo-NMOS circuit using devices already available in the circuit and modifying the circuit connections thereto.
摘要翻译：提供了一种方法和装置，用于使得能够将多米诺骨牌电路转换成静态电路，而不需要重新设计芯片或集成电路掩模组。多米诺骨牌电路掩模可以被设计为包括适当的额外的未连接的设备，其可以通过仅改变互连掩模而在芯片设计释放之后被添加或连接到电路中。备用器件可以添加并选择性地用于使多米诺骨电路金属掩模可编程成逻辑等效的静态电路。在第一示例性方法中，添加额外的设备，和/或将现有设备重新连接在多米诺骨牌电路中以形成互补的等效静态门。在第二示例性方法中，使用电路中已经可用的设备并修改其电路连接，将多米诺骨电路转换成伪NMOS电路。

6. 发明授权

US6037804A Reduced power dynamic logic circuit that inhibits reevaluation of stable inputs 失效
标题翻译：减少功率动态逻辑电路，抑制稳定输入的重新评估
公开(公告)号：US6037804A
公开(公告)日：2000-03-14
申请号：US049741
申请日：1998-03-27
申请人： Christopher McCall Durham , Visweswara Rao Kodali , Michael Ju Hyeok Lee , Douglas Ele Martin , Harsh Dev Sharma
发明人： Christopher McCall Durham , Visweswara Rao Kodali , Michael Ju Hyeok Lee , Douglas Ele Martin , Harsh Dev Sharma
IPC分类号： H03K19/00 , H03K19/096 , H03K19/094
CPC分类号： H03K19/096 , H03K19/0016
摘要： A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.
摘要翻译：降低功率的集成电路包括电路数据输入，电路数据输出和至少一行动态逻辑。动态逻辑行包括行时钟输入，行数据输入和耦合到电路数据输出的行数据输出，其中根据电路数据输入的值导出在行数据输入处接收的值。集成电路还包括比较器，其比较电路数据输入端的当前值和先前值，以及开关，其选择性地将在行时钟输入处接收的行时钟信号设置为非活动状态，并将行时钟信号暂时保持在非活动状态对比较器的响应检测到电路数据输入端的当前先前值是等效的。因此，动态逻辑行（并不需要）重新评估电路数据输入值，并降低功耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式