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1. 发明申请

US20130332146A1 High Speed Large Scale Dictionary Matching 有权
标题翻译：高速大字典匹配
公开(公告)号：US20130332146A1
公开(公告)日：2013-12-12
申请号：US13490832
申请日：2012-06-07
申请人： Kanak B. Agarwal , Harm P. Hofstee
发明人： Kanak B. Agarwal , Harm P. Hofstee
IPC分类号： G06F17/21
CPC分类号： G06F17/2735
摘要： A mechanism is provided for dictionary matching. The mechanism loads a plurality of dictionary memory arrays with a set of dictionary words and updates a plurality of status arrays. Each status array of the plurality of status arrays corresponds to a respective one of the plurality of dictionary memory arrays. Each entry of a given status array stores a status bit, which indicates whether a corresponding entry of the corresponding dictionary memory array stores a valid dictionary word. The mechanism receives an input data word and generates a hash value based on the input data word. The mechanism reads a dictionary word from each of the dictionary memory arrays and a status bit from each of the status arrays using the hash value as a read address. The mechanism determines whether a dictionary memory array within the plurality of dictionary memory arrays stores a valid dictionary word that matches the input data word.
摘要翻译：提供了字典匹配的机制。该机构使用一组字典字加载多个字典存储器阵列并更新多个状态阵列。多个状态阵列中的每个状态阵列对应于多个字典存储器阵列中的相应一个。给定状态阵列的每个条目存储状态位，其指示对应的字典存储器阵列的相应条目是否存储有效的字典字。该机制接收输入数据字，并根据输入数据字生成哈希值。该机制使用散列值作为读取地址从每个字典存储器阵列读取字典字，并从每个状态数组中读取状态位。该机构确定多个字典存储器阵列内的字典存储器阵列是否存储与输入数据字匹配的有效字典字。

2. 发明申请

US20070300115A1 APPARATUS AND METHOD FOR ACCELERATING TEST, DEBUG AND FAILURE ANALYSIS OF A MULTIPROCESSOR DEVICE 审中-公开
标题翻译：用于加速多处理器设备的测试，调试和故障分析的装置和方法
公开(公告)号：US20070300115A1
公开(公告)日：2007-12-27
申请号：US11421518
申请日：2006-06-01
申请人： Ramyanshu Datta , Matthew E. Fernsler , Harm P. Hofstee
发明人： Ramyanshu Datta , Matthew E. Fernsler , Harm P. Hofstee
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/2236
摘要： An apparatus and method for accelerating test, debug and failure analysis of a multiprocessor device are provided. With the apparatus and method, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault.
摘要翻译：提供了一种用于加速多处理器设备的测试，调试和故障分析的设备和方法。利用该装置和方法，利用片上跟踪逻辑来从多处理器设备的模块中提供的逻辑接收内部信号。这些模块优选地是彼此的副本，使得在给定相同的输入的情况下，每个模块应该以相同的方式操作并产生相同的输出，只要模块正常运行即可。模块提供相同的输入，并使用片上跟踪总线和片上跟踪逻辑分析仪跟踪模块的内部信号，以执行跟踪。将来自一个模块的内部信号与另一个模块进行比较，以确定是否存在指示故障的差异。可以对额外的模块对进行比较，以确定故障源的故障模块。

3. 发明授权

US08830714B2 High speed large scale dictionary matching 有权
标题翻译：高速大字典匹配
公开(公告)号：US08830714B2
公开(公告)日：2014-09-09
申请号：US13490832
申请日：2012-06-07
申请人： Kanak B. Agarwal , Harm P. Hofstee
发明人： Kanak B. Agarwal , Harm P. Hofstee
IPC分类号： G11C15/00 , G06F17/30
CPC分类号： G06F17/2735
摘要： A mechanism is provided for dictionary matching. The mechanism loads a plurality of dictionary memory arrays with a set of dictionary words and updates a plurality of status arrays. Each status array of the plurality of status arrays corresponds to a respective one of the plurality of dictionary memory arrays. Each entry of a given status array stores a status bit, which indicates whether a corresponding entry of the corresponding dictionary memory array stores a valid dictionary word. The mechanism receives an input data word and generates a hash value based on the input data word. The mechanism reads a dictionary word from each of the dictionary memory arrays and a status bit from each of the status arrays using the hash value as a read address. The mechanism determines whether a dictionary memory array within the plurality of dictionary memory arrays stores a valid dictionary word that matches the input data word.
摘要翻译：提供了字典匹配的机制。该机构使用一组字典字加载多个字典存储器阵列并更新多个状态阵列。多个状态阵列中的每个状态阵列对应于多个字典存储器阵列中的相应一个。给定状态阵列的每个条目存储状态位，其指示对应的字典存储器阵列的相应条目是否存储有效的字典字。该机制接收输入数据字，并根据输入数据字生成哈希值。该机制使用散列值作为读取地址从每个字典存储器阵列读取字典字，并从每个状态数组中读取状态位。该机构确定多个字典存储器阵列内的字典存储器阵列是否存储与输入数据字匹配的有效字典字。

4. 发明申请

US20130148745A1 High Bandwidth Decompression of Variable Length Encoded Data Streams 有权
公开(公告)号：US20130148745A1
公开(公告)日：2013-06-13
申请号：US13313072
申请日：2011-12-07
申请人： Kanak B. Agarwal , Harm P. Hofstee , Damir A. Jamsek , Andrew K. Martin
发明人： Kanak B. Agarwal , Harm P. Hofstee , Damir A. Jamsek , Andrew K. Martin
IPC分类号： H04B1/66
CPC分类号： H03M7/30
摘要： Mechanisms are provided for decoding a variable length encoded data stream. A decoder of a data processing system receives an input line of data. The input line of data is a portion of the variable length encoded data stream. The decoder determines an amount of bit spill over of the input line of data onto a next input line of data. The decoder aligns the input line of data to begin at a symbol boundary based on the determined amount of bit spill over. The decoder tokenizes the aligned input line of data to generate a set of tokens. Each token corresponds to an encoded symbol in the aligned next input line of data. The decoder generates an output word of data based on the set of tokens. The output word of data corresponds to a word of data in the original set of data.

5. 发明申请

US20120246354A1 Multithreaded Programmable Direct Memory Access Engine 有权
标题翻译：多线程可编程直接存储器访问引擎
公开(公告)号：US20120246354A1
公开(公告)日：2012-09-27
申请号：US13488856
申请日：2012-06-05
申请人： Brian K. Flachs , Harm P. Hofstee , Charles R. Johns , Matthew E. King , John S. Liberty , Brad W. Michael
发明人： Brian K. Flachs , Harm P. Hofstee , Charles R. Johns , Matthew E. King , John S. Liberty , Brad W. Michael
IPC分类号： G06F13/28
CPC分类号： G06F9/30087 , G06F9/3877 , G06F13/1663 , G06F13/28
摘要： A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.
摘要翻译：提供了编程作为多线程处理器操作的直接存储器访问引擎的机制。从与直接存储器访问引擎相关联的本地存储器中的主机处理器接收多个程序。在来自主机处理器的直接存储器访问引擎中接收到指示将要执行位于本地存储器中的多个程序的请求。直接存储器访问引擎在主机处理器的干预下执行多个程序中的两个或多个。当多个程序中的两个或更多个程序中的每一个完成执行时，直接存储器访问引擎向主处理器发送指示程序已经完成执行的完成通知。

6. 发明申请

US20100082941A1 DELEGATED VIRTUALIZATION IN A MULTI-CORE PROCESSOR (MCP) 有权
标题翻译：多核处理器（MCP）中的代表虚拟化
公开(公告)号：US20100082941A1
公开(公告)日：2010-04-01
申请号：US12241332
申请日：2008-09-30
申请人： Karl J. Duvalsaint , Harm P. Hofstee , Daeik Kim , Moon J. Kim
发明人： Karl J. Duvalsaint , Harm P. Hofstee , Daeik Kim , Moon J. Kim
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/5027 , G06F2209/509 , Y02D10/22
摘要： The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs delegate functionality to one or more groups of SPEs such that those group(s) of SPEs will act as pseudo MPEs. The pseudo MPEs will utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.
摘要翻译：本公开应用于具有一组（例如，一个或多个）控制元件（例如，MPE）和一组子处理元件（例如，SPE）的通用微处理器架构。在这种安排下，MPEs和SPE的组织方式是使用较少数量的MPE使用体现为一组虚拟控制线程的程序代码控制一组SPE的行为。该安排还使MPEs能够将功能委托给一个或多个SPE组，使得这些SPE组将充当伪MPE。伪MPE将利用伪虚拟化控制线程来控制其他组的SPE的行为。在典型的实施例中，该装置包括耦合到与核耦合的电源的MCP以向每个核（或核心组）提供电源电压以及控制数字元件和子处理元件的多个实例。

7. 发明申请

US20080229166A1 Accelerating Test, Debug and Failure Analysis of a Multiprocessor Device 失效
标题翻译：加速多处理器设备的测试，调试和故障分析
公开(公告)号：US20080229166A1
公开(公告)日：2008-09-18
申请号：US12129030
申请日：2008-05-29
申请人： Ramyanshu Datta , Matthew E. Fernsler , Harm P. Hofstee
发明人： Ramyanshu Datta , Matthew E. Fernsler , Harm P. Hofstee
IPC分类号： G01R31/28 , G06F11/25
CPC分类号： G06F11/2236
摘要： A mechanism for accelerating test, debug and failure analysis of a multiprocessor device is provided. With the mechanism, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault.
摘要翻译：提供了一种用于加速多处理器设备的测试，调试和故障分析的机制。利用该机制，利用片上跟踪逻辑来从多处理器设备的模块中提供的逻辑接收内部信号。这些模块优选地是彼此的副本，使得在给定相同的输入的情况下，每个模块应该以相同的方式操作并产生相同的输出，只要模块正常运行即可。模块提供相同的输入，并使用片上跟踪总线和片上跟踪逻辑分析仪跟踪模块的内部信号，以执行跟踪。将来自一个模块的内部信号与另一个模块进行比较，以确定是否存在指示故障的差异。可以对额外的模块对进行比较，以确定故障源的故障模块。

8. 发明授权

US06541847B1 Packaging for multi-processor shared-memory system 失效
公开(公告)号：US06541847B1
公开(公告)日：2003-04-01
申请号：US10066999
申请日：2002-02-04
申请人： Harm P. Hofstee , Eric A. Johnson , Randall J. Stutzman , Jamil A. Wakil
发明人： Harm P. Hofstee , Eric A. Johnson , Randall J. Stutzman , Jamil A. Wakil
IPC分类号： H01L2302
CPC分类号： H01L25/18 , H01L23/3735 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/09701
摘要： An electrical structure or package, and associated method of formation. A plurality of logic chips is coupled electrically to a memory chip either through conductive members (e.g., solder balls) that interface with the memory chip and each logic chip, or through a sequential logic-to-memory electrically conductive path that includes: a first conductive member electrically coupled to a logic chip; an electrically conductive via path through a circuitized substrate; and a second conductive member electrically coupled to the memory chip. The logic chips are electrically coupled to the substrate either directly through an interfacing solder interconnection from the logic chip to the substrate, or indirectly through the memory chip such that the memory chip is electrically coupled to the substrate by an interfacing solder interconnect. The electrical structure may be plugged into a socket of a backplane of a circuit card.

9. 发明授权

US08824569B2 High bandwidth decompression of variable length encoded data streams 有权
公开(公告)号：US08824569B2
公开(公告)日：2014-09-02
申请号：US13313072
申请日：2011-12-07
申请人： Kanak B. Agarwal , Harm P. Hofstee , Damir A. Jamsek , Andrew K. Martin
发明人： Kanak B. Agarwal , Harm P. Hofstee , Damir A. Jamsek , Andrew K. Martin
IPC分类号： H04B1/66
CPC分类号： H03M7/30
摘要： Mechanisms are provided for decoding a variable length encoded data stream. A decoder of a data processing system receives an input line of data. The input line of data is a portion of the variable length encoded data stream. The decoder determines an amount of bit spill over of the input line of data onto a next input line of data. The decoder aligns the input line of data to begin at a symbol boundary based on the determined amount of bit spill over. The decoder tokenizes the aligned input line of data to generate a set of tokens. Each token corresponds to an encoded symbol in the aligned next input line of data. The decoder generates an output word of data based on the set of tokens. The output word of data corresponds to a word of data in the original set of data.

10. 发明授权

US08341638B2 Delegated virtualization across physical partitions of a multi-core processor (MCP) 有权
标题翻译：授权虚拟化跨多核处理器（MCP）的物理分区
公开(公告)号：US08341638B2
公开(公告)日：2012-12-25
申请号：US12241697
申请日：2008-09-30
申请人： Karl J. Duvalsaint , Harm P. Hofstee , Daeik Kim , Moon J. Kim
发明人： Karl J. Duvalsaint , Harm P. Hofstee , Daeik Kim , Moon J. Kim
IPC分类号： G06F9/46 , G06F9/44 , G06F13/00 , G06F7/38 , H04L12/56
CPC分类号： G06F9/4893 , G06F2209/483 , Y02D10/24
摘要： This disclosure describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization across physical boundaries that define physical partitions in a symmetric MCP. Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). The arrangement also enables MPEs to delegate functionality to one or more groups of SPEs such that those group(s) of SPEs may act as pseudo MPEs. Such delegation may occur across the physical boundaries. Regardless, the pseudo MPEs may utilize pseudo virtualized control threads to control the behavior of other groups of SPEs also across physical boundaries.
摘要翻译：本公开描述了用于MPE的装置，计算机体系结构，方法，操作系统，编译器和应用程序产品，以及跨物理边界的虚拟化，其定义对称MCP中的物理分区。除其他之外，本公开应用于具有一组（例如，一个或多个）控制/主处理元件（例如MPE）和一组子处理元件（例如SPE）的通用微处理器架构。该安排还使MPE能够将功能委派给一个或多个SPE组，使得那些SPE组可以充当伪MPE。这种授权可能会跨物理边界发生。无论如何，伪MPE可以利用伪虚拟化控制线程来控制物理边界上的其他SPE组的行为。

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