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1. 发明授权

US06269463B1 Method and system for automatically determining transparency behavior of non-scan cells for combinational automatic test pattern generation 有权
标题翻译：用于自动确定非扫描单元的组合自动测试图案生成的透明度行为的方法和系统
公开(公告)号：US06269463B1
公开(公告)日：2001-07-31
申请号：US09283310
申请日：1999-03-31
申请人： Suryanarayana Duggirala , Harihara Ganesan , Cyrus Hay
发明人： Suryanarayana Duggirala , Harihara Ganesan , Cyrus Hay
IPC分类号： G06F1100
CPC分类号： G01R31/31725 , G01R31/318364 , G01R31/318378 , G01R31/318583 , G01R31/318594
摘要： A method and system for generating test vectors for testing scan-based sequential circuits that contain non-scan cells using combinational ATPG techniques. The present invention includes the computer implemented step of receiving a netlist description of an integrated circuit device that comprises scan cells and non-scannable cells. Under certain conditions, some non-scan cells may exhibit sequential transparency behavior. The present invention identifies such conditions and characterizes each non-scan cell as sequentially transparent or non-transparent. Based on such characterization, the present invention transforms non-scan cells exhibiting sequential transparency behavior with transparent logic models during combinational ATPG (Automatic Test Pattern Generation) analysis. Because non-scan cells of exhibiting sequential transparency behavior are not replaced with “force-to-X” models, the fault coverage of the test patterns thus generated is significantly improved.
摘要翻译：一种用于生成测试向量的方法和系统，用于使用组合ATPG技术测试包含非扫描单元的基于扫描的顺序电路。本发明包括计算机实现的步骤，用于接收包括扫描单元和不可扫描单元的集成电路设备的网表描述。在某些条件下，一些非扫描单元可能表现出顺序的透明性。本发明识别这样的条件并且将每个非扫描单元的特征化为依次透明或不透明。基于这种表征，本发明在组合ATPG（自动测试模式生成）分析期间，利用透明逻辑模型来转换呈现顺序透明度行为的非扫描单元。由于表现顺序透明度行为的非扫描单元未被“强制到X”模型所替代，所以生成的测试图案的故障覆盖率得到显着改善。

2. 发明授权

US07454726B2 Technique for generating input stimulus to cover properties not covered in random simulation 有权
标题翻译：用于产生输入刺激以覆盖随机模拟中未涵盖的属性的技术
公开(公告)号：US07454726B2
公开(公告)日：2008-11-18
申请号：US11353672
申请日：2006-02-13
申请人： William K. Lam , Yick Kei Wong , Harihara Ganesan
发明人： William K. Lam , Yick Kei Wong , Harihara Ganesan
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318342 , G01R31/318357 , G06F11/261
摘要： A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property is evaluated, and dependent on the evaluation, the simulation trace is dumped and stored for subsequent exercising of the cover directive.
摘要翻译：首先使用有向和/或随机测试案例来验证集成电路的设计。对于未定义和/或随机测试用例覆盖的封面指令，将创建一个属性，其中导致属性失败的模拟跟踪覆盖了封面指令。此后，对该属性进行评估，并依赖于评估，将模拟轨迹转储并存储以用于后续行使封面指令。

3. 发明申请

US20070192753A1 Technique for generating input stimulus to cover properties not covered in random simulation 有权
标题翻译：用于产生输入刺激以覆盖随机模拟中未涵盖的属性的技术
公开(公告)号：US20070192753A1
公开(公告)日：2007-08-16
申请号：US11353672
申请日：2006-02-13
申请人： William Lam , Yick Wong , Harihara Ganesan
发明人： William Lam , Yick Wong , Harihara Ganesan
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318342 , G01R31/318357 , G06F11/261
摘要： A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where wherein a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property is evaluated, and dependent on the evaluation, the simulation trace is dumped and stored for subsequent exercising of the cover directive.
摘要翻译：首先使用有向和/或随机测试案例来验证集成电路的设计。对于未定义和/或随机测试用例覆盖的封面指令，将创建一个属性，其中导致属性失败的仿真跟踪覆盖了封面指令。此后，对该属性进行评估，并依赖于评估，将模拟轨迹转储并存储以用于后续行使封面指令。

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