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1. 发明申请

US20110244666A1 Methods Of Manufacturing Stair-Type Structures And Methods Of Manufacturing Nonvolatile Memory Devices Using The Same 审中-公开
标题翻译：制造楼梯型结构的方法和使用其制造非易失性存储器件的方法
公开(公告)号：US20110244666A1
公开(公告)日：2011-10-06
申请号：US13080288
申请日：2011-04-05
申请人： Ha-Na Kim , Gyungjin Min , Chulho Shin , Sukho Joo , Han Geun Yu , Yeonghun Han
发明人： Ha-Na Kim , Gyungjin Min , Chulho Shin , Sukho Joo , Han Geun Yu , Yeonghun Han
IPC分类号： H01L21/302 , H01L21/28 , H01L21/31
CPC分类号： H01L27/11578 , H01L21/033 , H01L21/0337 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11575
摘要： Methods of manufacturing stair-type structures and methods of manufacturing nonvolatile memory devices using the same. Methods of manufacturing stair-type structures may include forming a plurality of thin layers stacked in plate shapes, forming a mask on an utmost thin layer, patterning the utmost layer using the mask as an etch mask, escalating a width of the mask and etching each of the thin layers at a different width of the mask to form a stair-type structure of the thin layers. Control gates may be formed into the stair-type structures using the methods of manufacturing stair-type structures.
摘要翻译：制造楼梯型结构的方法和制造使用其的非易失性存储装置的制造方法。制造阶梯型结构的方法可以包括形成多个以板形形式堆叠的薄层，在最薄层上形成掩模，使用掩模将最大层图案化为蚀刻掩模，增加掩模的宽度并蚀刻每个在薄膜的不同宽度处的薄层，以形成薄层的阶梯型结构。可以使用制造楼梯型结构的方法将控制门形成为楼梯型结构。

2. 发明授权

US08557661B2 Methods of manufacturing a semiconductor device and a semiconductor memory device thereby 有权
标题翻译：因此制造半导体器件和半导体存储器件的方法
公开(公告)号：US08557661B2
公开(公告)日：2013-10-15
申请号：US13314627
申请日：2011-12-08
申请人： Han-Geun Yu , Gyung-Jin Min , Seong-Soo Lee , Suk-Ho Joo , Yoo-Chul Kong , Dae-Hyun Jang
发明人： Han-Geun Yu , Gyung-Jin Min , Seong-Soo Lee , Suk-Ho Joo , Yoo-Chul Kong , Dae-Hyun Jang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/11565 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L27/11575 , H01L27/11582
摘要： A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.
摘要翻译：一种制造半导体器件的方法包括在存储单元区域上形成存储单元，在连接区域上交替地形成牺牲层和绝缘中间层，以提供配置为电连接存储单元的布线，形成包括蚀刻掩模图案在顶部牺牲层上的元件，在每个蚀刻掩模图案元件的每个侧壁上形成阻挡侧壁，形成第一光致抗蚀剂图案，选择性地将第一阻挡侧壁从存储器单元区域最远地覆盖并覆盖其它阻挡侧壁，蚀刻暴露顶部牺牲层和绝缘中间层以暴露第二牺牲层，通过横向去除第一光致抗蚀剂图案至第二阻挡侧壁暴露的程度形成第二光致抗蚀剂图案，并将暴露的顶部和第二牺牲层和绝缘夹层蚀刻到形成一个楼梯形状 d侧边缘部分。

3. 发明申请

US20120187471A1 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR MEMORY DEVICE THEREBY 有权
标题翻译：制造半导体器件的方法和半导体存储器件
公开(公告)号：US20120187471A1
公开(公告)日：2012-07-26
申请号：US13314627
申请日：2011-12-08
申请人： Han-Geun YU , Gyung-Jin MIN , Seong-Soo LEE , Suk-Ho JOO , Yoo-Chul KONG , Dae-Hyun JANG
发明人： Han-Geun YU , Gyung-Jin MIN , Seong-Soo LEE , Suk-Ho JOO , Yoo-Chul KONG , Dae-Hyun JANG
IPC分类号： H01L29/78 , H01L21/336 , H01L21/308
CPC分类号： H01L27/11565 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L27/11575 , H01L27/11582
摘要： A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.
摘要翻译：一种制造半导体器件的方法包括在存储单元区域上形成存储单元，在连接区域上交替地形成牺牲层和绝缘中间层，以提供配置为电连接存储单元的布线，形成包括蚀刻掩模图案在顶部牺牲层上的元件，在每个蚀刻掩模图案元件的每个侧壁上形成阻挡侧壁，形成第一光致抗蚀剂图案，选择性地将第一阻挡侧壁从存储器单元区域最远地覆盖并覆盖其它阻挡侧壁，蚀刻暴露顶部牺牲层和绝缘中间层以暴露第二牺牲层，通过横向去除第一光致抗蚀剂图案至第二阻挡侧壁暴露的程度形成第二光致抗蚀剂图案，并将暴露的顶部和第二牺牲层和绝缘夹层蚀刻到形成一个楼梯形状 d侧边缘部分。

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