专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09312478B2 Magnetic devices and methods of manufacturing the same 有权
标题翻译：磁性器件及其制造方法
公开(公告)号：US09312478B2
公开(公告)日：2016-04-12
申请号：US13589708
申请日：2012-08-20
申请人： Hak-sun Lee , Tokashiki Ken , Myeong-cheol Kim , Hyung-joon Kwon , Sang-min Lee , Woo-cheol Lee , Myung-hoon Jung
发明人： Hak-sun Lee , Tokashiki Ken , Myeong-cheol Kim , Hyung-joon Kwon , Sang-min Lee , Woo-cheol Lee , Myung-hoon Jung
IPC分类号： H01L21/3065 , H01L43/12 , B81C1/00 , B82Y10/00 , B82Y25/00 , G11B5/31 , H01L27/22
CPC分类号： H01L43/12 , B81C1/00531 , B82Y10/00 , B82Y25/00 , G11B5/3163 , H01L21/3065 , H01L27/228 , Y10T428/24479
摘要： Magnetic devices, and methods of manufacturing the same, include a stack structure including at least one magnetic layer, etched using an etching gas including at least 70 volume percent of a hydrogen-containing gas and at least 2 volume percent of CO gas.
摘要翻译：磁性器件及其制造方法包括使用包括至少70体积％的含氢气体和至少2体积％的CO气体的蚀刻气体蚀刻的至少一个磁性层的堆叠结构。

2. 发明申请

US20130149499A1 MAGNETIC DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：磁性装置及其制造方法
公开(公告)号：US20130149499A1
公开(公告)日：2013-06-13
申请号：US13589708
申请日：2012-08-20
申请人： Hak-sun LEE , Tokashiki KEN , Myeong-cheol KIM , Hyung-joon KWON , Sang-min LEE , Woo-cheol LEE , Myung-hoon JUNG
发明人： Hak-sun LEE , Tokashiki KEN , Myeong-cheol KIM , Hyung-joon KWON , Sang-min LEE , Woo-cheol LEE , Myung-hoon JUNG
IPC分类号： G11C11/02 , B32B3/30
CPC分类号： H01L43/12 , B81C1/00531 , B82Y10/00 , B82Y25/00 , G11B5/3163 , H01L21/3065 , H01L27/228 , Y10T428/24479
摘要： Magnetic devices, and methods of manufacturing the same, include a stack structure including at least one magnetic layer, etched using an etching gas including at least 70 volume percent of a hydrogen-containing gas and at least 2 volume percent of CO gas.
摘要翻译：磁性器件及其制造方法包括使用包括至少70体积％的含氢气体和至少2体积％的CO气体的蚀刻气体蚀刻的至少一个磁性层的堆叠结构。

3. 发明申请

US20080220611A1 Method of forming fine patterns of semiconductor devices using double patterning 有权
标题翻译：使用双重图案形成半导体器件的精细图案的方法
公开(公告)号：US20080220611A1
公开(公告)日：2008-09-11
申请号：US12073502
申请日：2008-03-06
申请人： Kyung-yub Jeon , Myeong-cheol Kim , Doo-youl Lee , Hak-sun Lee
发明人： Kyung-yub Jeon , Myeong-cheol Kim , Doo-youl Lee , Hak-sun Lee
IPC分类号： H01L21/308
CPC分类号： H01L21/31144 , H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate.
摘要翻译：根据示例性实施例的形成半导体器件的精细图案的方法可以包括通过将待蚀刻的蚀刻膜上的第一掩模图案和缓冲掩模图案堆叠在衬底上来形成多个多层掩模图案，在蚀刻在多个多层掩模图案之间的空间中的膜，第二掩模图案，去除第二掩模图案以暴露第一掩模图案的上表面，以及通过使用第一和第二掩模图案蚀刻蚀刻膜形成精细图案作为蚀刻掩模该示例性实施例可以导致在单个基板上以不同间距形成不同尺寸。

4. 发明授权

US08178408B2 Methods of manufacturing charge trap-type non-volatile memory devices 有权
标题翻译：制造电荷陷阱型非易失性存储器件的方法
公开(公告)号：US08178408B2
公开(公告)日：2012-05-15
申请号：US12651781
申请日：2010-01-04
申请人： Hak-Sun Lee , Kyoung-Sub Shin , Jeong-Dong Choe
发明人： Hak-Sun Lee , Kyoung-Sub Shin , Jeong-Dong Choe
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L27/11568
摘要： Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer.
摘要翻译：一些方法涉及制造电荷陷阱型非易失性存储器件。可以形成在衬底中沿第一方向延伸的隔离层图案。通过使邻近隔离层图案的基板的暴露表面凹陷而在基板中形成凹部单元。隧道绝缘层和电荷陷阱层依次形成在基板上。图案化隧道绝缘层和电荷陷阱层，通过蚀刻衬底的限定区域，隔离层图案，隧道绝缘层，隔离层状图案，隔离层状图案，隧道绝缘层，并且电荷陷阱层直到设置在凹陷单元的底表面上的电荷陷阱层的顶表面与隔离层图案的顶表面对准。形成了覆盖电荷陷阱层图案，隔离层图案和插入在电荷阱图案之间的基板的限定区域的阻挡绝缘层。在阻挡绝缘层上形成面对电荷陷阱层图案的栅电极图案。该制造过程可以减小单元存储单元之间的电荷扩展和/或可以防止/避免阻塞绝缘层的击穿电压的降低。

5. 发明授权

US08003469B2 Method of manufacturing non-volatile semiconductor devices 有权
标题翻译：制造非易失性半导体器件的方法
公开(公告)号：US08003469B2
公开(公告)日：2011-08-23
申请号：US12611362
申请日：2009-11-03
申请人： Hak-Sun Lee , Kyoung-Sub Shin
发明人： Hak-Sun Lee , Kyoung-Sub Shin
IPC分类号： H01L21/336
CPC分类号： H01L27/11573
摘要： A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.
摘要翻译：非易失性半导体器件包括在衬底的第一区域中的存储单元，在衬底的第二区域中的低电压晶体管，以及在衬底的第三区域中的高压晶体管。存储单元包括形成在基板上的隧道绝缘层，形成在基板的第一区域中的隧道绝缘层上的电荷俘获层图案，形成在电荷俘获层图案上的阻挡层图案和形成在基板上的控制栅极阻挡层图案。控制栅极的宽度显着小于阻挡层图案的宽度，并且控制栅极的宽度基本上小于电荷俘获层图案的宽度。此外，在控制栅极和阻挡层图案之间形成偏移，使得在控制栅极的侧壁上未形成间隔物。

6. 发明授权

US07998874B2 Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same 有权
标题翻译：用于形成具有细间距的硬掩模图案的方法和使用其形成半导体器件的方法
公开(公告)号：US07998874B2
公开(公告)日：2011-08-16
申请号：US11978719
申请日：2007-10-30
申请人： Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon , Cha-won Koh , Ji-young Lee
发明人： Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon , Cha-won Koh , Ji-young Lee
IPC分类号： H01L21/461 , C03C15/00
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088
摘要： A method for forming hard mask patterns includes, sequentially forming first, second, and third hard mask layers formed of materials having different etching selectivities on a substrate, forming first sacrificial patterns having a first pitch therebetween on the third hard mask layer, forming fourth hard mask patterns with a second pitch between the first sacrificial patterns, the second pitch being substantially equal to about ½ of the first pitch, patterning the third hard mask layer to form third hard mask patterns using the fourth hard mask patterns as an etch mask, patterning the second hard mask layer to form second hard mask patterns using the third and fourth hard mask patterns as an etch mask, and patterning the first hard mask layer to form first hard mask patterns with the second pitch therebetween using the second and third hard mask patterns as an etch mask.
摘要翻译：一种形成硬掩模图案的方法包括：在基板上顺序地形成由具有不同蚀刻选择性的材料形成的第一，第二和第三硬掩模层，在第三硬掩模层上形成具有第一间距的第一牺牲图案，形成第四硬在第一牺牲图案之间具有第二间距的掩模图案，第二间距基本上等于第一间距的大约1/2，使用第四硬掩模图案作为蚀刻掩模，图案化第三硬掩模层以形成第三硬掩模图案，图案化第二硬掩模层，以使用第三和第四硬掩模图案作为蚀刻掩模形成第二硬掩模图案，以及使用第二和第三硬掩模图案使第一硬掩模层形成第一硬掩模图案，其间具有第二间距，作为蚀刻掩模。

7. 发明授权

US07935635B2 Method of forming fine patterns of semiconductor devices using double patterning 有权
标题翻译：使用双重图案形成半导体器件的精细图案的方法
公开(公告)号：US07935635B2
公开(公告)日：2011-05-03
申请号：US12073502
申请日：2008-03-06
申请人： Kyung-yub Jeon , Myeong-cheol Kim , Doo-youl Lee , Hak-sun Lee
发明人： Kyung-yub Jeon , Myeong-cheol Kim , Doo-youl Lee , Hak-sun Lee
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31144 , H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate.
摘要翻译：根据示例性实施例的形成半导体器件的精细图案的方法可以包括通过将待蚀刻的蚀刻膜上的第一掩模图案和缓冲掩模图案堆叠在衬底上来形成多个多层掩模图案，在蚀刻在多个多层掩模图案之间的空间中的膜，第二掩模图案，去除第二掩模图案以暴露第一掩模图案的上表面，以及通过使用第一和第二掩模图案蚀刻蚀刻膜形成精细图案作为蚀刻掩模该示例性实施例可以导致在单个基板上以不同间距形成不同尺寸。

8. 发明申请

US20100112768A1 METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR DEVICES 有权
标题翻译：制造非易失性半导体器件的方法
公开(公告)号：US20100112768A1
公开(公告)日：2010-05-06
申请号：US12611362
申请日：2009-11-03
申请人： Hak-Sun LEE , Kyoung-Sub Shin
发明人： Hak-Sun LEE , Kyoung-Sub Shin
IPC分类号： H01L21/336
CPC分类号： H01L27/11573
摘要： A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.
摘要翻译：非易失性半导体器件包括在衬底的第一区域中的存储单元，在衬底的第二区域中的低电压晶体管，以及在衬底的第三区域中的高压晶体管。存储单元包括形成在基板上的隧道绝缘层，形成在基板的第一区域中的隧道绝缘层上的电荷俘获层图案，形成在电荷俘获层图案上的阻挡层图案和形成在基板上的控制栅极阻挡层图案。控制栅极的宽度显着小于阻挡层图案的宽度，并且控制栅极的宽度基本上小于电荷俘获层图案的宽度。此外，在控制栅极和阻挡层图案之间形成偏移，使得在控制栅极的侧壁上未形成间隔物。

9. 发明授权

US07550391B2 Method for forming fine patterns of a semiconductor device using double patterning 有权
标题翻译：使用双重图案形成半导体器件的精细图案的方法
公开(公告)号：US07550391B2
公开(公告)日：2009-06-23
申请号：US11730292
申请日：2007-03-30
申请人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee , Je-woo Han
发明人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee , Je-woo Han
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088 , H01L21/32139 , Y10S438/947
摘要： A method for forming fine patterns of a semiconductor device is disclosed. The method includes forming an etch film on a substrate, forming a protection film on the etch film, forming a hard mask layer on the protection film, and forming a plurality of first mask patterns characterized by a first pitch on the hard mask layer. The method further comprises forming a plurality of second mask patterns, forming hard mask patterns exposing portions of the protection film by etching the hard mask layer using the first and second mask patterns as an etch mask, and removing the first and second mask patterns. The method still further comprises exposing portions of the etch film and forming a plurality of fine patterns characterized by a second pitch equal to half of the first pitch by etching the etch film using at least the hard mask patterns as an etch mask.
摘要翻译：公开了一种用于形成半导体器件的精细图案的方法。该方法包括在衬底上形成蚀刻膜，在蚀刻膜上形成保护膜，在保护膜上形成硬掩模层，以及在硬掩模层上形成以第一间距为特征的多个第一掩模图案。该方法还包括形成多个第二掩模图案，通过使用第一和第二掩模图案作为蚀刻掩模蚀刻硬掩模层，形成暴露部分保护膜的硬掩模图案，以及去除第一和第二掩模图案。该方法还包括暴露部分蚀刻膜并且通过使用至少硬掩模图案作为蚀刻掩模蚀刻蚀刻膜来形成多个精细图案，其特征在于具有等于第一间距的一半的第二间距。

10. 发明申请

US20080188083A1 Method of forming fine patterns of semiconductor device using double patterning 有权
标题翻译：使用双重图案形成半导体器件精细图案的方法
公开(公告)号：US20080188083A1
公开(公告)日：2008-08-07
申请号：US11810200
申请日：2007-06-05
申请人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee
发明人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/32137
摘要： A method of forming fine patterns of a semiconductor device includes double etching by changing a quantity of producing polymer by-products to etch a film with different thicknesses in regions having different pattern densities. In a first etching, reactive ion etching (RIE) is performed upon a buffer layer and a hardmask layer both in a low-density pattern region and a high-density pattern region under a first etching ambient until an etch film is exposed in the low-density pattern region using mask patterns as an etch mask. In second etching for forming the hardmask patterns, using the mask patterns as an etch mask, the hardmask layer is etched until the etch film is exposed in the high-density pattern region while accumulating polymer by-products on the etch film in the low-density pattern region under a second etching ambient having polymer by-products produced greater than in the first etching ambient.
摘要翻译：形成半导体器件的精细图案的方法包括通过改变产生聚合物副产物的量来双重蚀刻，以在具有不同图案密度的区域中蚀刻具有不同厚度的膜。在第一蚀刻中，在第一蚀刻环境下，在低密度图案区域和高密度图案区域中的缓冲层和硬掩模层上执行反应离子蚀刻（RIE），直到蚀刻膜暴露于低使用掩模图案作为蚀刻掩模的密度图案区域。在用于形成硬掩模图案的第二蚀刻中，使用掩模图案作为蚀刻掩模，硬掩模层被蚀刻直到蚀刻膜在高密度图案区域中暴露，同时在低密度图案区域中的聚合物副产物上积累在蚀刻膜上，在第二蚀刻环境下具有比在第一蚀刻环境中产生的聚合物副产物大的密度图案区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式