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1. 发明授权

US07998874B2 Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same 有权
标题翻译：用于形成具有细间距的硬掩模图案的方法和使用其形成半导体器件的方法
公开(公告)号：US07998874B2
公开(公告)日：2011-08-16
申请号：US11978719
申请日：2007-10-30
申请人： Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon , Cha-won Koh , Ji-young Lee
发明人： Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon , Cha-won Koh , Ji-young Lee
IPC分类号： H01L21/461 , C03C15/00
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088
摘要： A method for forming hard mask patterns includes, sequentially forming first, second, and third hard mask layers formed of materials having different etching selectivities on a substrate, forming first sacrificial patterns having a first pitch therebetween on the third hard mask layer, forming fourth hard mask patterns with a second pitch between the first sacrificial patterns, the second pitch being substantially equal to about ½ of the first pitch, patterning the third hard mask layer to form third hard mask patterns using the fourth hard mask patterns as an etch mask, patterning the second hard mask layer to form second hard mask patterns using the third and fourth hard mask patterns as an etch mask, and patterning the first hard mask layer to form first hard mask patterns with the second pitch therebetween using the second and third hard mask patterns as an etch mask.
摘要翻译：一种形成硬掩模图案的方法包括：在基板上顺序地形成由具有不同蚀刻选择性的材料形成的第一，第二和第三硬掩模层，在第三硬掩模层上形成具有第一间距的第一牺牲图案，形成第四硬在第一牺牲图案之间具有第二间距的掩模图案，第二间距基本上等于第一间距的大约1/2，使用第四硬掩模图案作为蚀刻掩模，图案化第三硬掩模层以形成第三硬掩模图案，图案化第二硬掩模层，以使用第三和第四硬掩模图案作为蚀刻掩模形成第二硬掩模图案，以及使用第二和第三硬掩模图案使第一硬掩模层形成第一硬掩模图案，其间具有第二间距，作为蚀刻掩模。

2. 发明申请

US20080131793A1 Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same 有权
标题翻译：用于形成具有细间距的硬掩模图案的方法和使用其形成半导体器件的方法
公开(公告)号：US20080131793A1
公开(公告)日：2008-06-05
申请号：US11978719
申请日：2007-10-30
申请人： Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon , Cha-won Koh , Ji-young Lee
发明人： Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon , Cha-won Koh , Ji-young Lee
IPC分类号： G03F7/40 , G03F1/00
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088
摘要： A method for forming hard mask patterns includes, sequentially forming first, second, and third hard mask layers formed of materials having different etching selectivities on a substrate, forming first sacrificial patterns having a first pitch therebetween on the third hard mask layer, forming fourth hard mask patterns with a second pitch between the first sacrificial patterns, the second pitch being substantially equal to about ½ of the first pitch, patterning the third hard mask layer to form third hard mask patterns using the fourth hard mask patterns as an etch mask, patterning the second hard mask layer to form second hard mask patterns using the third and fourth hard mask patterns as an etch mask, and patterning the first hard mask layer to form first hard mask patterns with the second pitch therebetween using the second and third hard mask patterns as an etch mask.
摘要翻译：一种形成硬掩模图案的方法包括：在基板上顺序地形成由具有不同蚀刻选择性的材料形成的第一，第二和第三硬掩模层，在第三硬掩模层上形成具有第一间距的第一牺牲图案，形成第四硬在第一牺牲图案之间具有第二间距的掩模图案，第二间距基本上等于第一间距的大约1/2，使用第四硬掩模图案作为蚀刻掩模，图案化第三硬掩模层以形成第三硬掩模图案，图案化第二硬掩模层，以使用第三和第四硬掩模图案作为蚀刻掩模形成第二硬掩模图案，以及使用第二和第三硬掩模图案使第一硬掩模层形成第一硬掩模图案，其间具有第二间距，作为蚀刻掩模。

3. 发明授权

US07576010B2 Method of forming pattern using fine pitch hard mask 有权
标题翻译：使用细间距硬掩模形成图案的方法
公开(公告)号：US07576010B2
公开(公告)日：2009-08-18
申请号：US11699476
申请日：2007-01-30
申请人： Ji-young Lee , Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon
发明人： Ji-young Lee , Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338
摘要： A method of forming a first hard mask pattern including a plurality of first line patterns formed on the etch target layer in a first direction and having a first pitch. A third layer is formed on sidewalls and an upper surface of the first hard mask pattern, such that the third layer includes a top surface having a recess formed between two adjacent first line patterns. A second hard mask pattern including a plurality of second line patterns each extending in the first direction within the recess is formed. Then, the third layer is anisotropically etched to selectively expose an etch target layer between the first line patterns and the second line patterns. Then, the etch target layer is anisotropically etched using the first hard mask pattern and the second hard mask pattern as an etch mask.
摘要翻译：一种形成第一硬掩模图案的方法，所述第一硬掩模图案包括在第一方向上形成在蚀刻目标层上并具有第一间距的多个第一线图案。第三层形成在第一硬掩模图案的侧壁和上表面上，使得第三层包括具有形成在两个相邻的第一线图案之间的凹部的顶表面。形成包括在凹部内沿第一方向延伸的多个第二线图案的第二硬掩模图案。然后，第三层被各向异性蚀刻以选择性地暴露第一线图案和第二线图案之间的蚀刻目标层。然后，使用第一硬掩模图案和第二硬掩模图案作为蚀刻掩模对蚀刻目标层进行各向异性蚀刻。

4. 发明申请

US20070123037A1 Method of forming pattern using fine pitch hard mask 有权
标题翻译：使用细间距硬掩模形成图案的方法
公开(公告)号：US20070123037A1
公开(公告)日：2007-05-31
申请号：US11699476
申请日：2007-01-30
申请人： Ji-young Lee , Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon
发明人： Ji-young Lee , Hak-sun Lee , Myeong-cheol Kim , Kyung-yub Jeon
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338
摘要： A method of forming a first hard mask pattern including a plurality of first line patterns formed on the etch target layer in a first direction and having a first pitch. A third layer is formed on sidewalls and an upper surface of the first hard mask pattern, such that the third layer includes a top surface having a recess formed between two adjacent first line patterns. A second hard mask pattern including a plurality of second line patterns each extending in the first direction within the recess is formed. Then, the third layer is anisotropically etched to selectively expose an etch target layer between the first line patterns and the second line patterns. Then, the etch target layer is anisotropically etched using the first hard mask pattern and the second hard mask pattern as an etch mask.
摘要翻译：一种形成第一硬掩模图案的方法，所述第一硬掩模图案包括在第一方向上形成在蚀刻目标层上并具有第一间距的多个第一线图案。第三层形成在第一硬掩模图案的侧壁和上表面上，使得第三层包括具有形成在两个相邻的第一线图案之间的凹部的顶表面。形成包括在凹部内沿第一方向延伸的多个第二线图案的第二硬掩模图案。然后，第三层被各向异性蚀刻以选择性地暴露第一线图案和第二线图案之间的蚀刻目标层。然后，使用第一硬掩模图案和第二硬掩模图案作为蚀刻掩模对蚀刻目标层进行各向异性蚀刻。

5. 发明申请

US20110269294A1 METHOD OF FORMING A HARD MASK AND METHOD OF FORMING A FINE PATTERN OF SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US20110269294A1
公开(公告)日：2011-11-03
申请号：US13181655
申请日：2011-07-13
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

6. 发明申请

US20100197139A1 METHOD OF FORMING A HARD MASK AND METHOD OF FORMING A FINE PATTERN OF SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US20100197139A1
公开(公告)日：2010-08-05
申请号：US12759771
申请日：2010-04-14
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

7. 发明授权

US07732341B2 Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US07732341B2
公开(公告)日：2010-06-08
申请号：US11727124
申请日：2007-03-23
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

8. 发明申请

US20080124931A1 Method for forming fine patterns of a semiconductor device using a double patterning process 失效
标题翻译：使用双重图案形成工艺形成半导体器件的精细图案的方法
公开(公告)号：US20080124931A1
公开(公告)日：2008-05-29
申请号：US11978718
申请日：2007-10-30
申请人： Doo-youl Lee , Pan-suk Kwak , Sung-gon Jung , Jung-hyeon Lee , Suk-joo Lee , Cha-won Koh , Ji-young Lee
发明人： Doo-youl Lee , Pan-suk Kwak , Sung-gon Jung , Jung-hyeon Lee , Suk-joo Lee , Cha-won Koh , Ji-young Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76838
摘要： A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.
摘要翻译：用于形成半导体器件的精细图案的方法包括在具有第一和第二区域的衬底上形成蚀刻膜，在衬底上形成第一掩模图案以在第一区域中具有第一图案密度，在第二区域中形成第二图案密度在所述第一掩模图案之间形成第一封盖图案，在所述第一掩模图案之间形成第二封盖图案，使得在第二封盖图案之间形成凹陷区域，并且使得第一蚀刻图案被限定为包括所述第一和第二封盖图案，在凹陷区域中形成第二掩模图案以包括第一和第二掩模图案，去除第一和第二蚀刻图案中的一个，使得在基板上残留单个蚀刻图案，并使用剩余的蚀刻图案蚀刻蚀刻膜作为蚀刻掩模以形成蚀刻膜图案。

9. 发明授权

US07892982B2 Method for forming fine patterns of a semiconductor device using a double patterning process 失效
标题翻译：使用双重图案形成工艺形成半导体器件的精细图案的方法
公开(公告)号：US07892982B2
公开(公告)日：2011-02-22
申请号：US11978718
申请日：2007-10-30
申请人： Doo-youl Lee , Pan-suk Kwak , Sung-gon Jung , Jung-hyeon Lee , Suk-joo Lee , Cha-won Koh , Ji-young Lee
发明人： Doo-youl Lee , Pan-suk Kwak , Sung-gon Jung , Jung-hyeon Lee , Suk-joo Lee , Cha-won Koh , Ji-young Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76838
摘要： A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.
摘要翻译：用于形成半导体器件的精细图案的方法包括在具有第一和第二区域的衬底上形成蚀刻膜，在衬底上形成第一掩模图案以在第一区域中具有第一图案密度，在第二区域中形成第二图案密度在所述第一掩模图案之间形成第一封盖图案，在所述第一掩模图案之间形成第二封盖图案，使得在第二封盖图案之间形成凹陷区域，并且使得第一蚀刻图案被限定为包括所述第一和第二封盖图案，在凹陷区域中形成第二掩模图案以包括第一和第二掩模图案，去除第一和第二蚀刻图案中的一个，使得在基板上残留单个蚀刻图案，并使用剩余的蚀刻图案蚀刻蚀刻膜作为蚀刻掩模以形成蚀刻膜图案。

10. 发明申请

US20080076070A1 Methods of Forming Fine Patterns In Integrated Circuits Using Atomic Layer Deposition 审中-公开
标题翻译：在使用原子层沉积的集成电路中形成精细图案的方法
公开(公告)号：US20080076070A1
公开(公告)日：2008-03-27
申请号：US11554324
申请日：2006-10-30
申请人： Cha-won Koh , Han-ku Cho , Gi-sung Yeo , Yool Kang , Ji-young Lee , Doo-youl Lee
发明人： Cha-won Koh , Han-ku Cho , Gi-sung Yeo , Yool Kang , Ji-young Lee , Doo-youl Lee
IPC分类号： G03F7/00
CPC分类号： H01L21/31144 , H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76816
摘要： A fine pattern is formed in an integrated circuit substrate, by forming a sacrificial pattern on the integrated circuit substrate. The sacrificial pattern includes tops and side walls. Atomic layer deposition is then performed to atomic layer deposit a mask material layer on the sacrificial pattern, including on the tops and the side walls thereof, and on the integrated circuit substrate therebetween. The mask material layer that was atomic layer deposited is then etched, to expose the top and the integrated circuit therebetween, such that a mask material pattern remains on the side walls. The sacrificial pattern is then removed, and the integrated circuit substrate is then etched through the mask material pattern that remains.
摘要翻译：通过在集成电路基板上形成牺牲图案，在集成电路基板上形成精细图案。牺牲图案包括顶部和侧壁。然后进行原子层沉积以在牺牲图案上沉积掩模材料层，包括在其顶部和侧壁上以及其间的集成电路基板上。然后蚀刻原子层沉积的掩模材料层，以暴露其间的顶部和集成电路，使得掩模材料图案残留在侧壁上。然后去除牺牲图案，然后通过保留的掩模材料图案蚀刻集成电路基板。

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