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1. 发明授权

US09666586B2 CMOS compatible memory cells 有权
公开(公告)号：US09666586B2
公开(公告)日：2017-05-30
申请号：US14459403
申请日：2014-08-14
申请人： Gil Asa
发明人： Gil Asa
IPC分类号： H01L29/74 , H01L27/11 , H01L21/265 , H01L29/10 , H01L29/06 , G11C11/412 , H01L27/02
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/26513 , H01L27/0207 , H01L29/0653 , H01L29/1095
摘要： A memory cell and a process for production thereof, the memory cell having a CMOS substrate having two adjacent wells of opposite conductivity types, having trench isolation between the wells, wherein one of the wells is connected to a ground voltage level and the other one to a constant voltage level; a shallow lightly doped n layer in a first one of the wells; a shallow lightly doped p layer in a second one of the wells; at least a first and second deep heavily doped p regions in the first well; at least a first and second deep heavily doped n regions in the second well; and a conductor to connect the first and second deep p regions, the shallow n region, the first and second deep n regions and the shallow p region to the same input voltage level relative to the ground voltage level.

2. 发明申请

US20160049403A1 CMOS COMPATIBLE MEMORY CELLS 审中-公开
标题翻译： CMOS兼容记忆体
公开(公告)号：US20160049403A1
公开(公告)日：2016-02-18
申请号：US14459403
申请日：2014-08-14
申请人： Gil ASA
发明人： Gil ASA
IPC分类号： H01L27/092 , H01L27/11 , H01L29/10 , H01L29/06 , H01L21/265 , H01L21/8238
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/26513 , H01L27/0207 , H01L29/0653 , H01L29/1095
摘要： A memory cell and a process for production thereof, the memory cell having a CMOS substrate having two adjacent wells of opposite conductivity types, having trench isolation between the wells, wherein one of the wells is connected to a ground voltage level and the other one to a constant voltage level; a shallow lightly doped n layer in a first one of the wells; a shallow lightly doped p layer in a second one of the wells; at least a first and second deep heavily doped p regions in the first well; at least a first and second deep heavily doped n regions in the second well; and a conductor to connect the first and second deep p regions, the shallow n region, the first and second deep n regions and the shallow p region to the same input voltage level relative to the ground voltage level.
摘要翻译：一种存储单元及其制造方法，所述存储单元具有具有相反导电类型的两个相邻阱的CMOS衬底，在所述阱之间具有沟槽隔离，其中所述阱中的一个连接到接地电压电平，恒定电压电平; 在第一个孔中的浅轻掺杂n层; 在第二个孔中的浅的轻掺杂p层; 第一阱中的至少第一和第二深重掺杂p区; 至少第二阱中的第一和第二深度重掺杂的n区; 以及用于将第一和第二深p区，浅n区，第一和第二深n区和浅p区连接到相对于接地电压电平相同输入电压电平的导体。

3. 发明授权

US07330081B1 Digitally controlled oscillator and associated method 有权
标题翻译：数字振荡器及相关方法
公开(公告)号：US07330081B1
公开(公告)日：2008-02-12
申请号：US11178130
申请日：2005-07-07
申请人： Gil Asa , David Moshe , Ido Bourstein
发明人： Gil Asa , David Moshe , Ido Bourstein
IPC分类号： H03B5/04 , H03B5/24 , H03K3/03 , H03L1/00 , H03L5/02
CPC分类号： H03K3/0315 , H03K2005/00039 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143
摘要： A digitally controlled oscillator circuit is provided that comprises a ring oscillator including multiple inverters; multiple digitally controlled capacitors (DCCs), each coupled to apply a digitally controllable amount of capacitance to an output of a different one of the inverters; and control circuitry operable to change an amount of capacitance applied to each inverter during operation of the ring oscillator and to cause the multiple DCCs to apply substantially the same amounts of capacitance to each of the inverter throughout operation of the ring oscillator.
摘要翻译：提供了一种数字控制振荡器电路，其包括具有多个反相器的环形振荡器; 多个数字控制电容器（DCC），每个耦合以将数字可控量的电容施加到不同的逆变器的输出端; 以及控制电路，其可操作以在所述环形振荡器的操作期间改变施加到每个反相器的电容量，并且使得所述多个DCC在所述环形振荡器的操作期间对每个所述逆变器施加基本上相同量的电容。

4. 发明授权

US08837204B2 Four-transistor and five-transistor BJT-CMOS asymmetric SRAM cells 有权
标题翻译：四晶体管和五晶体管BJT-CMOS非对称SRAM单元
公开(公告)号：US08837204B2
公开(公告)日：2014-09-16
申请号：US13201461
申请日：2010-02-15
申请人： Gil Asa
发明人： Gil Asa
IPC分类号： G11C11/00
CPC分类号： H01L21/8249 , G11C11/411 , G11C11/412 , H01L27/0623 , H01L27/0688 , H01L27/1025 , H01L27/11 , H03K3/288
摘要： A memory cell comprises asymmetric retention elements formed of bipolar junction transistors integrated with a CMOS transistor. The BJT transistors of the retention element may be vertically stacked. In one embodiment, the N region of two adjacent NPN BJT transistors may be connected to ground and may form a common emitter of the NPN BJT transistors while the P region of two adjacent PNP BJT transistors may be connected to high voltage and may form a common emitter of the PNP BJT transistors. For further compactness in one embodiment a base of one transistor doubles as a collector of another transistor. The retention element may have only a single bit line and a single write line, with no negative bit line. In some embodiments, a single inverter and only three transistors may form the retention element. Memory space may be cut approximately in half.
摘要翻译：存储单元包括由与CMOS晶体管集成的双极结型晶体管形成的不对称保留元件。保持元件的BJT晶体管可以是垂直堆叠的。在一个实施例中，两个相邻NPN BJT晶体管的N区可以连接到地，并且可以形成NPN BJT晶体管的公共发射极，而两个相邻的PNP BJT晶体管的P区可以连接到高电压并且可以形成公共 PNP BJT晶体管的发射极。为了在一个实施例中进一步的紧凑性，一个晶体管的基极可兼作另一个晶体管的集电极。保持元件可以仅具有单个位线和单个写入线，没有负位线。在一些实施例中，单个逆变器和仅三个晶体管可以形成保持元件。内存空间大约可以削减一半。

5. 发明授权

US07667948B1 Digitally controlled oscillator and associated method 有权
标题翻译：数字振荡器及相关方法
公开(公告)号：US07667948B1
公开(公告)日：2010-02-23
申请号：US12069568
申请日：2008-02-11
申请人： Gil Asa , David Moshe , Ido Bourstein
发明人： Gil Asa , David Moshe , Ido Bourstein
IPC分类号： H01G4/00
CPC分类号： H03K3/0315 , H03K2005/00039 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143
摘要： A digitally controlled capacitor includes a first set of N capacitors, wherein the first set has a first capacitance value and each of the M capacitors has a second capacitance value, and at least one second set of N capacitors. The second set has the first capacitance value and each of the N capacitors has a third capacitance value that is greater than the second capacitance value. M and N are integers greater than one and M is not equal to N.
摘要翻译：数字控制电容器包括第一组N个电容器，其中第一组具有第一电容值，并且M个电容器中的每一个具有第二电容值，以及至少一个第二组N个电容器。第二组具有第一电容值，并且N个电容器中的每一个具有大于第二电容值的第三电容值。 M和N是大于1的整数，M不等于N.

6. 发明申请

US20070262377A1 Transistor Structure and Method of Manufacturing Thereof 审中-公开
标题翻译：晶体管结构及其制造方法
公开(公告)号：US20070262377A1
公开(公告)日：2007-11-15
申请号：US11667379
申请日：2005-11-10
申请人： Gil Asa
发明人： Gil Asa
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/66484 , H01L29/7831 , H01L29/7838 , H01L29/78648
摘要： Method of manufacturing and a transistor structure thereof comprising: a pair of spaced apart regions forming a source region and a drain region and defining at least part of a channel region there between, the source region and the drain region comprising a semiconductor heavily doped with n-type impurity element and said channel region comprising a semiconductor lightly doped with n-type impurity element; and a pair of gates each being insulated from the channel region by a respective gate insulating layer and being disposed substantially symmetrically along the channel region on opposite sides of thereof; whereby in use independent voltages may be applied to said gates so as to modify conductivity of the channel.
摘要翻译：制造方法及其晶体管结构包括：一对间隔开的区域，形成源极区域和漏极区域，并且在其间限定沟道区域的至少一部分，所述源极区域和漏极区域包括重掺杂有n 型杂质元素，所述沟道区包含轻掺杂n型杂质元素的半导体; 以及一对栅极，其各自通过相应的栅极绝缘层与沟道区域绝缘，并且沿着其相对侧上的沟道区域大致对称地设置; 由此在使用中可以将独立的电压施加到所述栅极，以便改变通道的电导率。

7. 发明申请

US20110299327A1 FOUR-TRANSISTOR AND FIVE-TRANSISTOR BJT-CMOS ASYMMETRIC SRAM CELLS 有权
标题翻译：四晶体和五晶体BJT-CMOS不对称SRAM电池
公开(公告)号：US20110299327A1
公开(公告)日：2011-12-08
申请号：US13201461
申请日：2010-02-15
申请人： Gil Asa
发明人： Gil Asa
IPC分类号： G11C11/34
CPC分类号： H01L21/8249 , G11C11/411 , G11C11/412 , H01L27/0623 , H01L27/0688 , H01L27/1025 , H01L27/11 , H03K3/288
摘要： A memory cell comprises asymmetric retention elements formed of bipolar junction transistors integrated with a CMOS transistor. The BJT transistors of the retention element may be vertically stacked. In one embodiment, the N region of two adjacent NPN BJT transistors may be connected to ground and may form a common emitter of the NPN BJT transistors while the P region of two adjacent PNP BJT transistors may be connected to high voltage and may form a common emitter of the PNP BJT transistors. For further compactness in one embodiment a base of one transistor doubles as a collector of another transistor. The retention element may have only a single bit line and a single write line, with no negative bit line. In some embodiments, a single inverter and only three transistors may form the retention element. Memory space may be cut approximately in half.
摘要翻译：存储单元包括由与CMOS晶体管集成的双极结型晶体管形成的不对称保留元件。保持元件的BJT晶体管可以是垂直堆叠的。在一个实施例中，两个相邻NPN BJT晶体管的N区可以连接到地，并且可以形成NPN BJT晶体管的公共发射极，而两个相邻的PNP BJT晶体管的P区可以连接到高电压并且可以形成公共 PNP BJT晶体管的发射极。为了在一个实施例中进一步的紧凑性，一个晶体管的基极可兼作另一个晶体管的集电极。保持元件可以仅具有单个位线和单个写入线，没有负位线。在一些实施例中，单个逆变器和仅三个晶体管可以形成保持元件。内存空间大约可以削减一半。

8. 发明授权

US07138850B1 High-gain synchronizer circuitry and methods 有权
标题翻译：高增益同步电路和方法
公开(公告)号：US07138850B1
公开(公告)日：2006-11-21
申请号：US10911454
申请日：2004-08-03
申请人： Gil Asa , David Moshe
发明人： Gil Asa , David Moshe
IPC分类号： G06G7/12
CPC分类号： H03K3/037 , H03K5/135
摘要： High-gain synchronizer circuitry and methods are provided that reduce the meta-stable resolve time of a synchronizer circuit. The high-gain synchronizer is made up of high-gain latch circuits. The high-gain latch circuits are made up of a series of inverters that at least initially increase in size and that are connected in a closed loop. In accordance with the invention, the time that the high-gain synchronizer remains in the meta-stable state is minimized through the use of the high-gain latch circuits.
摘要翻译：提供了高增益同步器电路和方法，可减少同步电路的元稳定解决时间。高增益同步器由高增益锁存电路组成。高增益锁存电路由一系列至少最初增加大小并且以闭环连接的逆变器组成。根据本发明，通过使用高增益锁存电路，使高增益同步器保持在元稳定状态的时间被最小化。

9. 发明专利

IL182868D0 TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING THEREOF 未知
公开(公告)号：IL182868D0
公开(公告)日：2007-08-19
申请号：IL18286807
申请日：2007-04-30
申请人： GIL ASA
IPC分类号： H01L20100101

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