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    • 2. 发明授权
    • Semiconductor package
    • 半导体封装
    • US08933552B2
    • 2015-01-13
    • US13312636
    • 2011-12-06
    • Gerald Krimmer
    • Gerald Krimmer
    • H01L29/72H01L23/31H01L23/16H01L23/495H01L23/00
    • H01L23/3107H01L23/16H01L23/49541H01L23/562H01L24/73H01L2224/32245H01L2224/48247H01L2224/73265H01L2924/14H01L2924/181H01L2924/00012H01L2924/00
    • In one embodiment, a semiconductor package comprising a metal base coupled to one or more pins, a semiconductor body having a top side and a bottom side, the top side comprising an integrated circuit and one or more metal surfaces for coupling the integrated circuit to the one more pins with one or more bonding wires, the bottom side non-positively coupled to the metal base, a disk having a top area and a base area, the base area coupled to the top side of the semiconductor body and at least partially covering the integrated circuit, the disk being electrically insulated from the semiconductor body, and a plastic compound completely enclosing the one or more bonding wires, and at least partially enclosing the top side of the integrated circuit, the top area of the disk, and the one or more pins.
    • 在一个实施例中,包括耦合到一个或多个引脚的金属基底的半导体封装,具有顶侧和底侧的半导体本体,所述顶侧包括集成电路和用于将所述集成电路耦合到所述集成电路的一个或多个金属表面 一个或多个具有一个或多个接合线的引脚,底侧不与金属基底连接,具有顶部区域和基底区域的盘,所述基底区域耦合到半导体本体的顶侧,并且至少部分地 覆盖集成电路,盘与半导体本体电绝缘,以及完全包围一个或多个接合线的塑料化合物,并且至少部分地封装集成电路的顶侧,盘的顶部区域和 一个或多个引脚。
    • 3. 发明申请
    • Semiconductor Package
    • 半导体封装
    • US20120161306A1
    • 2012-06-28
    • US13312636
    • 2011-12-06
    • Gerald Krimmer
    • Gerald Krimmer
    • H01L23/48
    • H01L23/3107H01L23/16H01L23/49541H01L23/562H01L24/73H01L2224/32245H01L2224/48247H01L2224/73265H01L2924/14H01L2924/181H01L2924/00012H01L2924/00
    • In one embodiment, a semiconductor package comprising a metal base coupled to one or more pins, a semiconductor body having a top side and a bottom side, the top side comprising an integrated circuit and one or more metal surfaces for coupling the integrated circuit to the one more pins with one or more bonding wires, the bottom side non-positively coupled to the metal base, a disk having a top area and a base area, the base area coupled to the top side of the semiconductor body and at least partially covering the integrated circuit, the disk being electrically insulated from the semiconductor body, and a plastic compound completely enclosing the one or more bonding wires, and at least partially enclosing the top side of the integrated circuit, the top area of the disk, and the one or more pins.
    • 在一个实施例中,包括耦合到一个或多个引脚的金属基底的半导体封装,具有顶侧和底侧的半导体本体,所述顶侧包括集成电路和用于将所述集成电路耦合到所述集成电路的一个或多个金属表面 一个或多个具有一个或多个接合线的引脚,底侧不与金属基底连接,具有顶部区域和基底区域的盘,所述基底区域耦合到半导体本体的顶侧,并且至少部分地 覆盖集成电路,盘与半导体本体电绝缘,以及完全包围一个或多个接合线的塑料化合物,并且至少部分地封装集成电路的顶侧,盘的顶部区域和 一个或多个引脚。