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1. 发明授权

US4438512A Method and apparatus for verifying storage apparatus addressing 失效
标题翻译：用于验证存储设备寻址的方法和装置
公开(公告)号：US4438512A
公开(公告)日：1984-03-20
申请号：US300414
申请日：1981-09-08
申请人： Michael H. Hartung , Richard E. Rieck , Gerald E. Tayler
发明人： Michael H. Hartung , Richard E. Rieck , Gerald E. Tayler
IPC分类号： G06F12/08 , G06F11/10 , G06F12/02 , G06F12/16 , G11C7/00 , G06F11/00
CPC分类号： G06F11/10 , G06F12/023
摘要： In a data storage system employing sequential data transfers for blocks of data bytes, an address offset is induced in the addressing mechanism such that each block transfer requires loading the address mechanism with an address of a block to be accessed. Address offset is preferably induced by inserting a blank register between adjacent blocks.
摘要翻译：在对数据字节块采用顺序数据传输的数据存储系统中，在寻址机制中引起地址偏移，使得每个块传输需要将地址机制加载到要访问的块的地址。优选地通过在相邻块之间插入空白寄存器来引起地址偏移。

2. 发明授权

US4636946A Method and apparatus for grouping asynchronous recording operations 失效
标题翻译：用于对异步记录操作进行分组的方法和装置
公开(公告)号：US4636946A
公开(公告)日：1987-01-13
申请号：US351835
申请日：1982-02-24
申请人： Michael H. Hartung , Gerald E. Tayler
发明人： Michael H. Hartung , Gerald E. Tayler
IPC分类号： G06F12/08 , G06F12/12 , G06F13/00
CPC分类号： G06F12/123 , G06F12/0804 , G06F12/0866 , G06F2212/312
摘要： The disclosure relates to demotion of data to a backing store (disk storage apparatus--DASD) from a random access cache in a peripheral data storage system. A cache replacement control list, such as a least recently used (LRU) list is scanned in a soon-to-be replaced first portion (portion closest to LRU entry) to identify first data to be demoted. Then the control list is scanned in first and second portions to identify further data to be demoted with the first data as a single group of data. In DASD, such data is all storable in the same cylinder of the DASD.
摘要翻译：本公开涉及从周边数据存储系统中的随机存取高速缓存向后备存储（磁盘存储装置-DASD）降级数据。在即将更换的第一部分（最接近LRU条目的部分）中扫描诸如最近最少使用（LRU）列表的高速缓存替换控制列表，以识别要降级的第一数据。然后在第一和第二部分中扫描控制列表，以将第一数据的另外的要降级的数据标识为单个数据组。在DASD中，这些数据都可以存储在DASD的同一个圆筒中。

3. 发明授权

US4633387A Load balancing in a multiunit system 失效
标题翻译：多单元系统中的负载均衡
公开(公告)号：US4633387A
公开(公告)日：1986-12-30
申请号：US469680
申请日：1983-02-25
申请人： Michael H. Hartung , Arthur H. Nolta , David G. Reed , Gerald E. Tayler
发明人： Michael H. Hartung , Arthur H. Nolta , David G. Reed , Gerald E. Tayler
IPC分类号： G06F3/06 , G06F12/00 , G06F12/08 , G06F13/10 , G06F13/14 , G06F15/16 , G06F15/177 , G06F15/00
CPC分类号： G06F12/0866 , G06F2212/312
摘要： In a multiunit data processing system, such as a multicontrol unit peripheral data storage system, a least busy one of the units requests work to be done from a busier unit. The busier unit, a work sending unit, supplies work to the work requesting or least busy unit. Work thresholds in the respective units determine when work is to be requested or transferred. In a data storage environment, the transferred work consists of data transfers to be achieved usually asynchronously to connected host activities, such as data transfers between a backing and a front store in a data storage hierarchy.
摘要翻译：在诸如多计算单元外围数据存储系统的多单元数据处理系统中，最繁忙的一个单元请求工作从繁忙的单元完成。繁忙的单位，工作发送单位，为工作请求或最不忙的单位提供工作。各单位的工作门槛确定何时要求或转移工作。在数据存储环境中，传输的工作包括通常与连接的主机活动异步进行的数据传输，例如数据存储层级中的后台和前端存储之间的数据传输。

4. 发明授权

US4430701A Method and apparatus for a hierarchical paging storage system 失效
标题翻译：分级寻呼存储系统的方法和装置
公开(公告)号：US4430701A
公开(公告)日：1984-02-07
申请号：US289631
申请日：1981-08-03
申请人： John H. Christian , Michael H. Hartung , Arthur H. Nolta , David G. Reed , Richard E. Rieck , Gerald E. Tayler , John S. Williams
发明人： John H. Christian , Michael H. Hartung , Arthur H. Nolta , David G. Reed , Richard E. Rieck , Gerald E. Tayler , John S. Williams
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0866 , G06F12/0888 , G06F2212/312
摘要： A plurality of addressable data storage devices are selectively directly accessed or accessed via a cache memory. Access via the cache memory uses one of a plurality of logical addresses; each of the data storage devices is represented by a plurality of the logical addresses. Each of the data storage devices can be reserved for direct access; such reservation does not apply to device accesses via the cache. Accesses to the devices are queued on a device basis.
摘要翻译：多个可寻址数据存储设备经由高速缓存存储器选择性地直接访问或访问。通过高速缓冲存储器的访问使用多个逻辑地址中的一个; 每个数据存储装置由多个逻辑地址表示。每个数据存储设备可以保留用于直接访问; 这种预留不适用于通过缓存的设备访问。对设备的访问在设备基础上排队。

5. 发明授权

US4956803A Sequentially processing data in a cached data storage system 失效
标题翻译：在缓存的数据存储系统中连续处理数据
公开(公告)号：US4956803A
公开(公告)日：1990-09-11
申请号：US407077
申请日：1989-09-14
申请人： Gerald E. Tayler , Robert E. Wagner
发明人： Gerald E. Tayler , Robert E. Wagner
IPC分类号： G06F12/08
CPC分类号： G06F12/0866 , G06F12/0862 , G06F12/0888 , G06F2212/312 , G06F2212/6026
摘要： The disclosure relates to sequential performance of a cached data storage subsystem with a minimal control signal processing. Sequential access is first detected by monitoring and examining the quantity of data accessed per unit of data storage (track) across a set of contiguously addressable tracks. Since the occupancy of the data in the cache is usually time limited, this examination provides an indication of the rate of sequential processing for a data set, i.e., a data set is being processed usually in contiguously addressable data storage units of a data storage system. Based upon the examination of a group of the tracks in a cache, the amount of data to be promoted to the cache from a backing store in anticipation of future host processor references is optimized. A promotion factor is calculated by combining the access extents monitored in the individual data storage areas and is expressed in a number of tracks units to be promoted. The examination of the group of tracks units and the implementation of the data promotion and demotion (early cast-out) is synchronized which results in a synergistic effect for increasing throughput of the cache for sequentially-processed data. A limit of promotion is determined to create a window of sequential data processing.
摘要翻译：本公开涉及具有最小控制信号处理的缓存数据存储子系统的顺序性能。首先通过监视和检查在一组可连续寻址的轨道上的每单位数据存储（轨道）访问的数据量来首先检测顺序访问。由于高速缓存中的数据的占用通常是时间限制的，所以该检查提供了数据集的顺序处理速率的指示，即数据集正在通过数据存储系统的连续可寻址数据存储单元进行处理。基于对高速缓存中的一组轨道的检查，优化了预期将来的主机处理器参考从待机存储器升级到高速缓存的数据量。通过组合在各个数据存储区域中监视的访问盘区来计算促销因子，并且以要提升的多个轨道单元表示。跟踪单元的检查和数据升级和降级（早期退出）的实现被同步，这导致对于递增的缓存的吞吐量的顺序处理的数据的协同效应。确定促销限制以创建顺序数据处理的窗口。

6. 发明授权

US4882642A Sequentially processing data in a cached data storage system 失效
标题翻译：在缓存的数据存储系统中连续处理数据
公开(公告)号：US4882642A
公开(公告)日：1989-11-21
申请号：US68857
申请日：1987-07-02
申请人： Gerald E. Tayler , Robert E. Wagner
发明人： Gerald E. Tayler , Robert E. Wagner
IPC分类号： G06F3/06 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0866 , G06F12/0862 , G06F12/0888 , G06F2212/312 , G06F2212/6026
摘要： The disclosure relates to sequential performance of a cached data storage subsystem with a minimal control signal processing. Sequential access is first detected by monitoring and examining the quantity of data accessed per unit of data storage (track) across a set of contiguously addressable tracks. Since the occupancy of the data in the cache is usually time limited, this examination provides an indication of the rate of sequential processing for a data set, i.e., a data set is being processed usually in contiguously addressable data storage units of a data storage system. Based upon the examination of a group of the tracks in a cache, the amount of data to be promoted to the cache from a backing store in anticipation of future host processor references is optimized. A promotion factor is calculated by combining the access extents monitored in the individual data storage areas and is expressed in a number of tracks units to be promoted. The examination of the group of tracks units and the implementation of the data promotion and demotion (early cast-out) is synchronized which results in a synergistic effect for increasing throughput of the cache for sequentially-processed data. A limit of promotion is determined to create a window of sequential data processing.

7. 发明授权

US5134563A Sequentially processing data in a cached data storage system 失效
标题翻译：在缓存的数据存储系统中连续处理数据
公开(公告)号：US5134563A
公开(公告)日：1992-07-28
申请号：US407078
申请日：1989-09-14
申请人： Gerald E. Tayler , Robert E. Wagner
发明人： Gerald E. Tayler , Robert E. Wagner
IPC分类号： G06F12/08
CPC分类号： G06F12/0866 , G06F12/0862 , G06F2212/312 , G06F2212/6026
摘要： The disclosure relates to sequential performance of a cached data storage subsystem with a minimal control signal processing. Sequential access is first detected by monitoring and examining the quantity of data accessed per unit of data storage (track) across a set of contiguously addressable tracks. Since the occupancy of the data in the cache is usually time limited, this examination provides an indication of the rate of sequential processing for a data set, i.e., a data set is being processed usually in contiguously addressable data storage units of a data storage system. Based upon the examination of a group of the tracks in a cache, the amount of data to be promoted to the cache from a backing store in anticipation of future host processor references is optimizied. A promotion factor is calculated by combining the access extents monitored in the individual data storage areas and is expressed in a number of tracks units to be promoted. The examination of the group of tracks units and the implementation of the data promotion and demotion (early cast-out) is synchronized which results in a synergistic effect for increasing throughput of the cache for sequentially-processed data. A limit of promotion is determined to create a window of sequential data processing.
摘要翻译：本公开涉及具有最小控制信号处理的缓存数据存储子系统的顺序性能。首先通过监视和检查在一组可连续寻址的轨道上的每单位数据存储（轨道）访问的数据量来首先检测顺序访问。由于高速缓存中的数据的占用通常是时间限制的，所以该检查提供了数据集的顺序处理速率的指示，即数据集正在通过数据存储系统的连续可寻址数据存储单元进行处理。基于对高速缓存中的一组轨道的检查，优化了预期将来的主机处理器引用将从后备存储器升级到高速缓存的数据量。通过组合在各个数据存储区域中监视的访问盘区来计算促销因子，并且以要提升的多个轨道单元表示。跟踪单元的检查和数据升级和降级（早期退出）的实现被同步，这导致对于递增的缓存的吞吐量的顺序处理的数据的协同效应。确定促销限制以创建顺序数据处理的窗口。

8. 发明授权

US4414644A Method and apparatus for discarding data from a buffer after reading such data 失效
标题翻译：在读取这些数据之后从缓冲器中丢弃数据的方法和装置
公开(公告)号：US4414644A
公开(公告)日：1983-11-08
申请号：US251005
申请日：1981-04-03
申请人： Gerald E. Tayler
发明人： Gerald E. Tayler
IPC分类号： G06F12/08 , G06F11/00 , G06F12/12 , G06F9/30
CPC分类号： G06F11/00 , G06F12/126
摘要： A two-level storage system selectively enables early discard of data from an upper level either immediately or at the end of a predetermined sequence of operation. A copy of data in such upper level is discarded immediately while altered copies of data are discarded at the end of the predetermined sequence of operations. Error conditions inhibit discarding altered data.
摘要翻译：两级存储系统可以选择性地使得能够立即或在预定操作顺序结束时从较高级别提前丢弃数据。这种较高级别的数据副本立即被丢弃，而数据的更改副本在预定操作顺序结束时被丢弃。错误条件可以阻止丢弃已更改的数据。

9. 发明授权

US4403288A Methods and apparatus for resetting peripheral devices addressable as a plurality of logical devices 失效
标题翻译：用于复位可寻址为多个逻辑设备的外围设备的方法和装置
公开(公告)号：US4403288A
公开(公告)日：1983-09-06
申请号：US306011
申请日：1981-09-28
申请人： John H. Christian , Arthur H. Nolta , David G. Reed , Richard E. Rieck , Gerald E. Tayler , Terrell N. Truan , John S. Williams
发明人： John H. Christian , Arthur H. Nolta , David G. Reed , Richard E. Rieck , Gerald E. Tayler , Terrell N. Truan , John S. Williams
IPC分类号： G06F11/14 , G06F12/08 , G06F13/00 , G06F13/12 , G06F11/00
CPC分类号： G06F13/122 , G06F12/0866
摘要： Direct access storage devices (DASD) are connected to a host via a cache. Each device can be independently addressed by any one of a plurality of addresses, also termed logical devices and exposures. Since operations between DASD and cache are combined for all of the independent logical devices, resetting operations related to one independent logical device can inadvertently interfere with operations of another independent logical device. To maintain data integrity, a programmed control accommodates logical device independence by using queues and control blocks relating to the DASD and logical devices, respectively.
摘要翻译：直接访问存储设备（DASD）通过缓存连接到主机。每个设备可以由多个地址中的任何一个地址（也称为逻辑设备和曝光）独立寻址。由于与所有独立逻辑设备组合DASD和缓存之间的操作，与一个独立的逻辑设备有关的复位操作可能会无意中干扰另一个独立逻辑设备的操作。为了保持数据完整性，编程控制通过分别使用与DASD和逻辑设备相关的队列和控制块来容纳逻辑设备独立性。

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