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1. 发明授权

US4577212A Structure for inhibiting forward bias beta degradation 失效
标题翻译：抑制正向偏压β降解的结构
公开(公告)号：US4577212A
公开(公告)日：1986-03-18
申请号：US626274
申请日：1984-06-29
申请人： Gary R. Hueckel , George S. Prokop
发明人： Gary R. Hueckel , George S. Prokop
IPC分类号： H01L29/73 , H01L21/3205 , H01L21/331 , H01L23/485 , H01L23/52 , H01L29/417 , H01L29/732 , H01L29/52 , H01L23/50 , H01L29/54
CPC分类号： H01L23/485 , H01L29/41708 , H01L2924/0002
摘要： An emitter contact structure is disclosed for alleviating forward bias beta degradation in a bipolar transistor. The structure comprises emitter contact metallurgy which travels over a dielectric insulating layer having an area of increased thickness adjacent to the area of contact between the metallurgy and the emitter.
摘要翻译：公开了用于减轻双极晶体管中的正向偏压β劣化的发射极接触结构。该结构包括发射极接触冶金，其在具有与冶金和发射体之间的接触面积相邻的厚度增加的区域的介电绝缘层上行进。

2. 发明授权

US6069051A Method of producing planar metal-to-metal capacitor for use in integrated circuits 失效
标题翻译：用于集成电路的平面金属 - 金属电容器的制造方法
公开(公告)号：US6069051A
公开(公告)日：2000-05-30
申请号：US668017
申请日：1996-06-17
申请人： Du B. Nguyen , Hazara S. Rathore , George S. Prokop , Richard A. Wachnik , Craig R. Gruszecki
发明人： Du B. Nguyen , Hazara S. Rathore , George S. Prokop , Richard A. Wachnik , Craig R. Gruszecki
IPC分类号： H01L21/02 , H01L21/768 , H01L21/20
CPC分类号： H01L28/40 , H01L21/76838 , H01L28/60 , Y10S438/945
摘要： A method of fabricating on chip metal-to-metal capacitors (MMCAP) uses planar processing with a flexible choice of dielectric, thickness and capacitor shape. The method provides a simpler process which has a better yield and more reliable structure by creating a metal-to-metal capacitor on a planar surface, not in deep trenches. In addition to the process simplicity, the method also allows the use of any dielectric materials which are needed by the product designer; e.g., higher or lower dielectric constant and also not limited by high etch rate difference. Because the inventive process is a planar process, there are no corners in the bottom of deep trenches to cause yield and reliability problems. The capacitor area can be adjusted to any shape because there are no edge effects.
摘要翻译：制造片上金属 - 金属电容器（MMCAP）的方法使用平面处理，具有电介质，厚度和电容器形状的灵活选择。该方法提供了一种更简单的方法，其在平坦表面上而不是在深沟槽中形成金属 - 金属电容器，具有更好的产量和更可靠的结构。除了工艺简单之外，该方法还允许使用产品设计者需要的任何介电材料; 例如更高或更低的介电常数，也不受高蚀刻速率差的限制。因为本发明的工艺是平面工艺，所以在深沟槽的底部没有角落以产生屈服和可靠性问题。电容器面积可以调整到任何形状，因为没有边缘效应。

3. 发明授权

US06730529B1 Method for chip testing 失效
标题翻译：芯片测试方法
公开(公告)号：US06730529B1
公开(公告)日：2004-05-04
申请号：US09236183
申请日：1999-01-25
申请人： Howard L. Kalter , H. Bernhard Pogge , George S. Prokop , Donald L. Wheater
发明人： Howard L. Kalter , H. Bernhard Pogge , George S. Prokop , Donald L. Wheater
IPC分类号： G01R3126
CPC分类号： H01L22/32 , G01R31/2884
摘要： Large area chip functionality is tested at an intermediate level in the manufacturing process. A process sequence is implemented in which a layer of insulator material is deposited over the chip. This layer is then processed to selectively open areas over existing vias which are to be used for chip level testing. The other vias remain covered with insulator. A sacrificial metal level is then deposited on the insulator layer and patterned to create adequately large test pad areas connected to exposed vias. This metal layer and the insulator layer covering the other buried vias are removed after testing to re-establish the full via set. As an extension to this basic test process, test circuits can be formed around or beside the chip to be tested in the kerf areas separating the chip from other chips on the semiconductor wafer. Connections to the test circuits is with a sacrificial metal layer over an insulator layer. The sacrificial metal layer and insulator layer are removed after testing. The test circuits are scribed off in the process of separating the chips after back end of line processing is completed.
摘要翻译：大面积芯片功能在制造过程的中间级别进行测试。实现了在芯片上沉积绝缘体材料层的工艺顺序。然后将该层处理成选择性地打开将用于芯片级测试的现有通孔上的区域。其他通孔仍然用绝缘体覆盖。然后将牺牲金属水平沉积在绝缘体层上并图案化以产生连接到暴露的通孔的足够大的测试焊盘区域。在测试之后，该金属层和覆盖另一埋孔的绝缘体层被重新建立完整的通孔。作为这个基本测试过程的延伸，测试电路可以在将芯片与半导体晶片上的其他芯片分开的切口区域中围绕或测试芯片周围形成。与测试电路的连接在绝缘体层上具有牺牲金属层。测试后去除牺牲金属层和绝缘体层。在线路处理后端完成之后分离芯片的过程中，划线测试电路。

4. 发明授权

US5899703A Method for chip testing 失效
标题翻译：芯片测试方法
公开(公告)号：US5899703A
公开(公告)日：1999-05-04
申请号：US827207
申请日：1997-03-28
申请人： Howard L. Kalter , H. Bernhard Pogge , George S. Prokop , Donald L. Wheater
发明人： Howard L. Kalter , H. Bernhard Pogge , George S. Prokop , Donald L. Wheater
IPC分类号： G01R31/28 , H01L23/58 , G01R31/26 , H01L21/66
CPC分类号： H01L22/32 , G01R31/2884
摘要： Large area chip functionality is tested at an intermediate level in the manufacturing process. A process sequence is implemented in which a layer of insulator material is deposited over the chip. This layer is then processed to selectively open areas over existing vias which are to be used for chip level testing. The other vias remain covered with insulator. A sacrificial metal level is then deposited on the insulator layer and patterned to create adequately large test pad areas connected to exposed vias. This metal layer and the insulator layer covering the other buried vias are removed after testing to re-establish the full via set. As an extension to this basic test process, test circuits can be formed around or beside the chip to be tested in the kerf areas separating the chip from other chips on the semiconductor wafer. Connections to the test circuits is with a sacrificial metal layer over an insulator layer. The sacrificial metal layer and insulator layer are removed after testing. The test circuits are scribed off in the process of separating the chips after back end of line processing is completed.
摘要翻译：大面积芯片功能在制造过程的中间级别进行测试。实现了在芯片上沉积绝缘体材料层的工艺顺序。然后将该层处理成选择性地打开将用于芯片级测试的现有通孔上的区域。其他通孔仍然用绝缘体覆盖。然后将牺牲金属水平沉积在绝缘体层上并图案化以产生连接到暴露的通孔的足够大的测试焊盘区域。在测试之后，该金属层和覆盖另一埋孔的绝缘体层被重新建立完整的通孔。作为这个基本测试过程的延伸，测试电路可以在将芯片与半导体晶片上的其他芯片分开的切口区域中围绕或测试芯片周围形成。与测试电路的连接在绝缘体层上具有牺牲金属层。测试后去除牺牲金属层和绝缘体层。在线路处理后端完成之后分离芯片的过程中，划线测试电路。

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