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    • 2. 发明申请
    • Method and system for managing cacheability of data blocks to improve processor power management
    • 用于管理数据块的高速缓存以提高处理器电源管理的方法和系统
    • US20070050549A1
    • 2007-03-01
    • US11217023
    • 2005-08-31
    • Gary Verdun
    • Gary Verdun
    • G06F12/00
    • G06F12/0888G06F2212/1028Y02D10/13
    • Systems and methods are disclosed for managing cacheability of data blocks to improve processor power management. Data can be intelligently moved between cache memory and non-cache memory based upon expected processing needs. Alternatively, the data can remain in the same memory space, and the memory designation can be intelligently managed from a cache memory to non-cache memory designation and/or from non-cache memory to cache memory designation depending upon the expected processing needs. In addition, both data movement and memory space re-designation can be utilized in conjunction. By intelligently managing the cacheability of the memory space holding the data blocks, processing efficiency and power management efficiency can be improved, particularly for bus master devices and related circuitry.
    • 公开了用于管理数据块的高速缓存以提高处理器电源管理的系统和方法。 可以根据预期的处理需要,在高速缓冲存储器和非缓存存储器之间智能地移动数据。 或者,数据可以保持在相同的存储器空间中,并且可以根据期望的处理需要将存储器指定从高速缓冲存储器智能地管理到非缓存存储器指定和/或从非高速缓存存储器缓存存储器指定。 另外,可以结合使用数据移动和存储器空间重新指定。 通过智能地管理保持数据块的存储器空间的可缓存性,可以提高处理效率和电源管理效率,特别是对于总线主设备和相关电路。
    • 3. 发明授权
    • System and method for reducing information handling system distributed capacitance
    • 减少信息处理系统分散电容的系统和方法
    • US07049754B2
    • 2006-05-23
    • US10885441
    • 2004-07-06
    • Gary Verdun
    • Gary Verdun
    • H05B37/00
    • H05B41/2822
    • The impact of distributed capacitance on information handling system operations is reduced by introducing an impedance element in series with the ground of the source of the distributed capacitance for an overall reduction of capacitance. For instance, distributed capacitance is formed between a liquid crystal display illumination lamp and ground through a reflector disposed proximate the lamp and aligned so that an interior reflecting surface directs light toward imaging pixels. An insulating dielectric added to the outer surface of reflector and assembled to information handling system chassis ground with some surface area in common between the reflector and the system ground form a separate series capacitor between the lamp and ground. The insulation dielectric capacitance combines in series with the reflector capacitance to provide a resultant capacitance of less than the reflector capacitance. Reduced distributed capacitance of the lamp and wiring to ground reduces power loss and improves illumination brightness distribution across the lamp.
    • 分布电容对信息处理系统操作的影响通过将阻抗元件与分布电容的源极接地串联以减小电容的整体而降低。 例如,通过设置在灯附近的反射器在液晶显示照明灯和地之间形成分布电容,并且对准,使得内部反射表面将光引向成像像素。 添加到反射器的外表面并组装到信息处理系统底盘接地的绝缘电介质,反射器和系统接地之间的一些共同的表面积在灯和地之间形成单独的串联电容器。 绝缘介质电容与反射器电容串联组合,以提供小于反射器电容的合成电容。 降低灯的分布电容和布线对地降低了功率损耗,并改善了整个灯的照明亮度分布。
    • 5. 发明授权
    • System and method for information handling system adaptive variable bus idle timer
    • 信息处理系统和方法自适应变量总线空闲定时器
    • US07647515B2
    • 2010-01-12
    • US11215260
    • 2005-08-29
    • Gary Verdun
    • Gary Verdun
    • G06F1/26G06F1/32
    • G06F1/3253G06F1/3228Y02D10/151
    • Power management of an information handling system PCI Express bus dynamically adjusts the inactivity time at the bus that is determined before initiation of a low power state by analyzing the transitions between low power and operating states over time. Dwell times of the bus in the low power state are compared with an inactivity goal to determine if the inactivity time should be adjusted up, such as when the bus enters the low power state too often, or should be adjusted down, such as when the bus enters the low power state too infrequently. In one embodiment, the dwell time is the time from entry into a low power state until initiation of the transition to an operating state and the inactivity goal is the time required for the bus to enter and exit the low power state.
    • 信息处理系统的电源管理PCI Express总线通过分析低功耗和工作状态随时间的转换,动态地调整在启动低功耗状态之前确定的总线上的不活动时间。 将处于低功率状态的总线的停留时间与不活动目标进行比较,以确定是否应该调整不活动时间,例如当总线频繁进入低功率状态时,或者应当将其调低,例如当 总线很少进入低功率状态。 在一个实施例中,停留时间是从进入低功率状态直到转换到操作状态的开始的时间,并且不活动目标是总线进入和退出低功率状态所需的时间。
    • 6. 发明申请
    • System and method for information handling system adaptive variable bus idle timer
    • 信息处理系统和方法自适应变量总线空闲定时器
    • US20070050653A1
    • 2007-03-01
    • US11215260
    • 2005-08-29
    • Gary Verdun
    • Gary Verdun
    • G06F1/26
    • G06F1/3253G06F1/3228Y02D10/151
    • Power management of an information handling system PCI Express bus dynamically adjusts the inactivity time at the bus that is determined before initiation of a low power state by analyzing the transitions between low power and operating states over time. Dwell times of the bus in the low power state are compared with an inactivity goal to determine if the inactivity time should be adjusted up, such as when the bus enters the low power state too often, or should be adjusted down, such as when the bus enters the low power state too infrequently. In one embodiment, the dwell time is the time from entry into a low power state until initiation of the transition to an operating state and the inactivity goal is the time required for the bus to enter and exit the low power state.
    • 信息处理系统的电源管理PCI Express总线通过分析低功耗和工作状态随时间的转换,动态地调整在启动低功耗状态之前确定的总线上的不活动时间。 将处于低功率状态的总线的停留时间与不活动目标进行比较,以确定是否应该调整不活动时间,例如当总线频繁进入低功率状态时,或者应当将其调低,例如当 总线很少进入低功率状态。 在一个实施例中,停留时间是从进入低功率状态直到转换到操作状态的开始的时间,并且不活动目标是总线进入和退出低功率状态所需的时间。