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1. 发明授权

US08395389B2 Lamp with metering device 有权
标题翻译：带计量装置的灯
公开(公告)号：US08395389B2
公开(公告)日：2013-03-12
申请号：US13036315
申请日：2011-02-28
申请人： Nedjip Orhan Tozun , Gabriel C. Risk , Samuel W. Goldman , Xianyi Wu , Erica D. Estrada
发明人： Nedjip Orhan Tozun , Gabriel C. Risk , Samuel W. Goldman , Xianyi Wu , Erica D. Estrada
IPC分类号： G01R31/00 , G01R11/63 , G01R21/00
CPC分类号： G01R22/06 , F21S9/026 , F21S9/037 , F21S9/043 , F21V33/00
摘要： A generator generates electricity by non-combustion means. A battery stores the generated electricity. An electrical appliance is powered by the stored electricity. A metering device tallies an operating parameter indicative of the amount of electrical energy consumed by the appliance. A housing supports the generator, the battery, the appliance and the metering device. A device, including the generator, the battery, the metering device and the housing, is manually portable.
摘要翻译：发电机通过非燃烧方式发电。电池存储发电。电器由存储电力供电。计量装置提供指示设备消耗的电能量的操作参数。外壳支撑发电机，电池，设备和计量装置。包括发电机，电池，计量装置和外壳的装置是手动便携式的。

2. 发明授权

US08249199B2 Low jitter and high bandwidth clock data recovery 有权
标题翻译：低抖动和高带宽时钟数据恢复
公开(公告)号：US08249199B2
公开(公告)日：2012-08-21
申请号：US12342825
申请日：2008-12-23
申请人： Drew G. Doblar , Dawei Huang , Gabriel C. Risk
发明人： Drew G. Doblar , Dawei Huang , Gabriel C. Risk
IPC分类号： H04L27/06
CPC分类号： H04L7/0062 , H04L7/0334 , H04L7/0337 , H04L7/10
摘要： A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus includes acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjusting a recovered clock phase based on the accumulated votes. A computer readable medium storing instructions to implement a low jitter and high bandwidth CDR apparatus, the instructions includes functionality to: acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjust recovered clock phase.
摘要翻译：实现低抖动和高带宽时钟和数据恢复（CDR）装置的方法包括获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 根据累计投票累积投票数，调整恢复时钟阶段。一种存储用于实现低抖动和高带宽CDR装置的指令的计算机可读介质，所述指令包括以下功能：获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 累积投票并调整恢复时钟阶段。

3. 发明授权

US08229048B2 Use of emphasis to equalize high speed signal quality 有权
标题翻译：使用重点来平衡高速信号质量
公开(公告)号：US08229048B2
公开(公告)日：2012-07-24
申请号：US12208898
申请日：2008-09-11
申请人： Gabriel C. Risk , Drew G. Doblar , Pruthvi A. Chaudhari
发明人： Gabriel C. Risk , Drew G. Doblar , Pruthvi A. Chaudhari
IPC分类号： H04B1/10
CPC分类号： H04L25/03012
摘要： A method, apparatus, and system for minimizing ringing in a high speed channel between a transmitter and a receiver in a circuit, including a component for initializing an n-tap equalization filter. The n-tap equalization filter includes numerous taps, each associated with each of numerous jitter pulses received from the transmitter at the receiver and over the channel. Many of the jitter pulses are greater than two. Further, each tap occurs at a time-domain point related to a time of a corresponding jitter pulse included within the numerous jitter pulses. Moreover, a component for applying the n-tap equalization filter to a subsequent signal sent over the channel is also included.
摘要翻译：一种用于最小化电路中的发射机和接收机之间的高速信道中的振铃的方法，装置和系统，包括用于初始化n抽头均衡滤波器的组件。 n抽头均衡滤波器包括多个抽头，每个抽头与接收器处的发射机和信道上的多个抖动脉冲中的每一个相关联。许多抖动脉冲大于2。此外，每个抽头发生在与包括在许多抖动脉冲内的相应抖动脉冲的时间相关的时域点。此外，还包括用于将n抽头均衡滤波器应用于通过信道发送的后续信号的分量。

4. 发明申请

US20090284261A1 Lamp With Metering Device 有权
标题翻译：带测光装置的灯
公开(公告)号：US20090284261A1
公开(公告)日：2009-11-19
申请号：US12122752
申请日：2008-05-19
申请人： Nedjip Orhan Tozun , Gabriel C. Risk , Samuel W. Goldman , Xianyi Wu , Erica D. Estrada
发明人： Nedjip Orhan Tozun , Gabriel C. Risk , Samuel W. Goldman , Xianyi Wu , Erica D. Estrada
IPC分类号： G01R31/00
CPC分类号： G01R22/06 , F21S9/026 , F21S9/037 , F21S9/043 , F21V33/00
摘要： A lamp includes a generator that generates electricity. A battery stores the generated electricity. A light source produces light from the stored electricity. A metering device tallies an operating parameter indicative of the amount of electrical energy consumed by the lamp.
摘要翻译：灯包括产生电的发电机。电池存储发电。光源产生来自储存电力的光。计量装置提供指示灯消耗的电能量的操作参数。

5. 发明授权

US07555085B1 CDR algorithms for improved high speed IO performance 有权
标题翻译： CDR算法，用于改进高速IO性能
公开(公告)号：US07555085B1
公开(公告)日：2009-06-30
申请号：US11209947
申请日：2005-08-23
申请人： Gabriel C. Risk , Naveen G. Malur , Jason H. Bau
发明人： Gabriel C. Risk , Naveen G. Malur , Jason H. Bau
IPC分类号： H04L7/00
CPC分类号： H04L7/0331 , H03L7/085 , H03L7/091 , H04L7/0083
摘要： A data receiver system. The system includes a clock generator configured to output a reference clock and circuitry configured to measure a direction of a phase difference between an input data stream and the reference clock. The circuitry is further configured to increment a counter if the phase difference is in a first direction, decrement the counter if the phase difference is in a direction opposite to the first direction, and convey a phase correction signal to the clock generator if an output value of the counter meets or exceeds a threshold. The clock generator is configured to adjust the phase of the reference clock in response to receiving the phase correction signal.
摘要翻译：数据接收系统。该系统包括时钟发生器，其被配置为输出参考时钟和被配置为测量输入数据流和参考时钟之间的相位差的方向的电路。电路还被配置为如果相位差处于第一方向则增加计数器，如果相位差在与第一方向相反的方向上则递减计数器，并将相位校正信号传送到时钟发生器，如果输出值的计数器达到或超过阈值。时钟发生器被配置为响应于接收到相位校正信号而调整参考时钟的相位。

6. 发明授权

US07533212B1 System memory board subsystem using DRAM with integrated high speed point to point links 有权
标题翻译：系统内存板子系统采用DRAM集成高速点对点链接
公开(公告)号：US07533212B1
公开(公告)日：2009-05-12
申请号：US11254948
申请日：2005-10-20
申请人： Drew G. Doblar , Gabriel C. Risk , Chung-Hsiao Wu
发明人： Drew G. Doblar , Gabriel C. Risk , Chung-Hsiao Wu
IPC分类号： G06F12/02
CPC分类号： G06F13/426
摘要： A memory system comprising memory modules including memory chips including integrated switching circuits. A memory controller coupled to the memory modules is configured to initiate memory accesses. When a switching circuit within a memory chip detects the memory access, the switching circuit routes the access to another memory module if the access is not directed to a memory chip of the receiving memory module, or processes the access locally if the access is directed to a memory chip of the receiving memory module. The memory controller and memory modules are coupled via bi-directional serial links. Each memory module may include multiple switching circuits, each of which may be coupled to fewer than all of the memory chips within the memory module. Switching circuits further include circuitry configured to de-serialize data prior to conveyance to a memory chip, and serialize data received from a DRAM chip prior to transmitting the received data.
摘要翻译：一种包括存储器模块的存储器系统，包括集成开关电路的存储器芯片。耦合到存储器模块的存储器控制器被配置为启动存储器访问。当存储器芯片内的开关电路检测到存储器访问时，如果访问不被引导到接收存储器模块的存储器芯片，则切换电路将访问路由到另一个存储器模块，或者如果访问指向接收存储器模块的存储芯片。存储器控制器和存储器模块通过双向串行链路耦合。每个存储器模块可以包括多个开关电路，每个开关电路可以耦合到比存储器模块内的所有存储器芯片少。开关电路还包括被配置为在传送到存储器芯片之前对数据进行反序列化的电路，以及在发送所接收的数据之前串行从DRAM芯片接收的数据。

7. 发明授权

US07437491B2 Clock and data recovery wherein an FB-DIMM is connected to signal path and null and sync frames control the FB-DIMM 有权
标题翻译：时钟和数据恢复，其中FB-DIMM连接到信号路径，空和同步帧控制FB-DIMM
公开(公告)号：US07437491B2
公开(公告)日：2008-10-14
申请号：US11265885
申请日：2005-11-02
申请人： Gabriel C. Risk , Dawei Huang , Jason H. Bau
发明人： Gabriel C. Risk , Dawei Huang , Jason H. Bau
IPC分类号： G06F3/00 , H04N7/00
CPC分类号： H04L7/0083 , H04L7/046 , H04L7/10 , H04L2007/045
摘要： Improved clock and data recovery involves transmitting one or more null frames prior to transmitting a sync frame. A receiving component detects for the sync frame to lock to a data signal sent on a signal path by a transmitting component. The one or more null frames transmitted prior to the sync frame results in a settling of the signal path prior to reception of the sync frame, thereby lessening or removing the effects of previously sent data on the sync frame.
摘要翻译：改进的时钟和数据恢复涉及在发送同步帧之前发送一个或多个空帧。接收组件检测同步帧锁定到由发射组件在信号路径上发送的数据信号。在同步帧之前发送的一个或多个空帧在接收到同步帧之前导致信号路径的建立，从而减少或消除先前在同步帧上发送的数据的影响。

8. 发明授权

US07636408B2 Reliable startup and steady-state of estimation based CDR and DFE 有权
标题翻译：基于CDR和DFE的可靠启动和稳定估计
公开(公告)号：US07636408B2
公开(公告)日：2009-12-22
申请号：US11445781
申请日：2006-06-01
申请人： Jason H. Bau , Drew G. Doblar , Gabriel C. Risk
发明人： Jason H. Bau , Drew G. Doblar , Gabriel C. Risk
IPC分类号： H04L7/00
CPC分类号： H04L25/03038 , H04L7/0004 , H04L7/0087 , H04L7/033 , H04L25/03057 , H04L25/03885 , H04L2025/03656 , H04L2025/03751 , H04L2025/03764
摘要： An apparatus and methods for recovering a clock and a data stream from a source synchronous input data stream are disclosed. The apparatus comprises a filter, a decision feedback equalizer (DFE), a phase error detector, and a clock generator. The input data stream is coupled to the filter and the DFE. The DFE synchronizes the input data stream to a clock generated by the clock generator. A filter output and a DFE output are each coupled to the phase error detector. During an initialization period, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the filter output and during a period of steady-state operation, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the DFE output. The output of the DFE comprises a recovered data stream.
摘要翻译：公开了一种用于从源同步输入数据流恢复时钟和数据流的装置和方法。该装置包括滤波器，判决反馈均衡器（DFE），相位误差检测器和时钟发生器。输入数据流耦合到滤波器和DFE。 DFE将输入数据流同步到时钟发生器产生的时钟。滤波器输出和DFE输出各自耦合到相位误差检测器。在初始化期间，相位误差检测器基于滤波器输出的一个或多个相位误差估计和在稳态运行期间向时钟发生器传送相位误差，相位误差检测器将相位误差传送到时钟基于DFE输出的一个或多个相位误差估计的发生器。 DFE的输出包括恢复的数据流。

9. 发明授权

US06932957B2 Method and apparatus for increasing bulk conductivity of a ferroelectric material 有权
公开(公告)号：US06932957B2
公开(公告)日：2005-08-23
申请号：US10187330
申请日：2002-06-28
申请人： Ronald O. Miles , Ludwig L. Galambos , Janos J. Lazar , Gabriel C. Risk , Alexei L. Alexandrovski , Gregory D. Miller , David Caudillo , Joseph M. McRae , Gisele L. Foulon
发明人： Ronald O. Miles , Ludwig L. Galambos , Janos J. Lazar , Gabriel C. Risk , Alexei L. Alexandrovski , Gregory D. Miller , David Caudillo , Joseph M. McRae , Gisele L. Foulon
IPC分类号： C30B31/06 , C01G33/00 , C01G35/00 , C01D15/00
CPC分类号： C01G33/00 , C01G35/00 , C01P2006/42
摘要： In one embodiment, a ferroelectric material is processed by placing the material in an environment including metal vapor and heating the material to a temperature below the Curie temperature of the material. This allows the bulk conductivity of the ferroelectric material to be increased without substantially degrading its ferroelectric domain properties. In one embodiment, the ferroelectric material comprises lithium tantalate and the metal vapor comprises zinc.

10. 发明申请

US20100158177A1 LOW JITTER AND HIGH BANDWIDTH CLOCK DATA RECOVERY 有权
标题翻译：低抖动和高带宽时钟数据恢复
公开(公告)号：US20100158177A1
公开(公告)日：2010-06-24
申请号：US12342825
申请日：2008-12-23
申请人： Drew G. Doblar , Dawei Huang , Gabriel C. Risk
发明人： Drew G. Doblar , Dawei Huang , Gabriel C. Risk
IPC分类号： H04L7/00
CPC分类号： H04L7/0062 , H04L7/0334 , H04L7/0337 , H04L7/10
摘要： A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus includes acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjusting a recovered clock phase based on the accumulated votes. A computer readable medium storing instructions to implement a low jitter and high bandwidth CDR apparatus, the instructions includes functionality to: acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjust recovered clock phase.
摘要翻译：实现低抖动和高带宽时钟和数据恢复（CDR）装置的方法包括获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 根据累计投票累积投票数，调整恢复时钟阶段。一种存储用于实现低抖动和高带宽CDR装置的指令的计算机可读介质，所述指令包括以下功能：获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 累积投票并调整恢复时钟阶段。

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