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1. 发明申请

WO2013095629A1 APPARATUS AND METHOD FOR VECTOR INSTRUCTIONS FOR LARGE INTEGER ARITHMETIC 审中-公开
标题翻译：用于大规模整数算术的矢量指令的装置和方法
公开(公告)号：WO2013095629A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067165
申请日：2011-12-23
申请人： INTEL CORPORATION , WOLRICH, Gilbert M. , YAP, Kirk S. , GUILFORD, James D. , OZTURK, Erdinc , GOPAL, Vinodh , FEGHALI, Wajdi K. , GULLEY, Sean M. , DIXON, Martin G.
发明人： WOLRICH, Gilbert M. , YAP, Kirk S. , GUILFORD, James D. , OZTURK, Erdinc , GOPAL, Vinodh , FEGHALI, Wajdi K. , GULLEY, Sean M. , DIXON, Martin G.
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/3016 , G06F7/525 , G06F7/57 , G06F9/3001 , G06F9/30036 , G06F9/3893
摘要： An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.
摘要翻译：描述了一种装置，其包括具有指令执行流水线的半导体芯片，该指令执行流水线具有一个或多个具有相应逻辑电路的执行单元，以便：a）执行将第一输入操作数与第二输入操作数相乘并且呈现下一部分的第一指令其中，第一和第二输入操作数是第一和第二输入向量的相应元素; b）执行第二指令，其将第一输入操作数和第二输入操作数相乘并呈现结果的上部，其中第一和第二输入操作数是第一和第二输入向量的相应元素; 以及c）执行加法指令，其中加法指令的相加的进位项被记录在掩码寄存器中。

2. 发明申请

WO2012078328A2 PATTERN MATCHING 审中-公开
标题翻译：模式匹配
公开(公告)号：WO2012078328A2
公开(公告)日：2012-06-14
申请号：PCT/US2011061088
申请日：2011-11-16
申请人： INTEL CORP , CLARK CHRISTOPHER F , GOPAL VINODH , WOLRICH GILBERT M
发明人： CLARK CHRISTOPHER F , GOPAL VINODH , WOLRICH GILBERT M
IPC分类号： G06F21/00
CPC分类号： G06F17/30985
摘要： An embodiment may include circuitry to determine, at least in part, whether one or more reference patterns are present in a data stream in a packet flow. The circuitry may include first pattern matching circuitry communicatively coupled to second pattern matching circuitry. The first pattern matching circuitry may determine, based at least in part upon one or more deterministic pattern matching operations, whether at least one portion of the one or more reference patterns is present in the stream. If the first pattern matching circuitry determines that the at least one portion of the one or more reference patterns is present in the stream, the second pattern matching circuitry may determine, based at least in part upon one or more pattern matching threads, whether at least one other portion of the one or more reference patterns is present in the stream. Many modifications are possible without departing from this embodiment.
摘要翻译：一个实施例可以包括用于至少部分地确定一个或多个参考模式是否存在于分组流中的数据流中的电路。该电路可以包括通信地耦合到第二模式匹配电路的第一模式匹配电路。第一模式匹配电路可至少部分地基于一个或多个确定性模式匹配操作来确定一个或多个参考模式的至少一部分是否存在于流中。如果第一模式匹配电路确定一个或多个参考模式的至少一部分存在于流中，则第二模式匹配电路可以至少部分地基于一个或多个模式匹配线确定是否至少一个或多个参考图案的另一部分存在于流中。在不脱离本实施例的情况下可以进行许多修改。

3. 发明申请

WO2011084214A2 METHOD AND APPARATUS FOR PERFORMING A SHIFT AND EXCLUSIVE OR OPERATION IN A SINGLE INSTRUCTION 审中-公开
标题翻译：在单一指令中执行移位和排除或操作的方法和装置
公开(公告)号：WO2011084214A2
公开(公告)日：2011-07-14
申请号：PCT/US2010054754
申请日：2010-10-29
申请人： INTEL CORP , GOPAL VINODH , GUILFORD JAMES D , OZTURK ERDINC , FEGHALI WAJDI , WOLRICH GILBERT M , DIXON MARTIN G
发明人： GOPAL VINODH , GUILFORD JAMES D , OZTURK ERDINC , FEGHALI WAJDI , WOLRICH GILBERT M , DIXON MARTIN G
IPC分类号： G06F9/305 , G06F13/14 , G06F13/16
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167 , G06F9/3816 , G06F9/3893
摘要： Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.
摘要翻译：用于执行换档和异或运算的方法和装置。在一个实施例中，一种装置包括执行第一指令的执行资源。响应于第一指令，所述执行资源对至少一个值执行移位和异或。

4. 发明申请

WO2007078923A2 CRYPTOGRAPHY PROCESSING UNITS AND MULTIPLIER 审中-公开
标题翻译：图像处理单元和多路复用器
公开(公告)号：WO2007078923A2
公开(公告)日：2007-07-12
申请号：PCT/US2006/048293
申请日：2006-12-18
申请人： INTEL CORPORATION , HASENPLAUGH, William, C. , CUTTER, Daniel, F. , FEGHALI, Wajdi, K. , WOLRICH, Gilbert, M. , GAUBATZ, Gunnar , GOPAL, Vinodh
发明人： HASENPLAUGH, William, C. , CUTTER, Daniel, F. , FEGHALI, Wajdi, K. , WOLRICH, Gilbert, M. , GAUBATZ, Gunnar , GOPAL, Vinodh
IPC分类号： G06F9/38
CPC分类号： G06F7/52 , G06F9/3001 , G06F9/3881 , G06F9/3885 , G06F21/72
摘要： In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.
摘要翻译：通常，在一个方面，本公开描述了包括多个可编程处理单元，专用硬件乘法器和连接多个处理单元和乘法器的至少一个总线的系统。

5. 发明申请

WO2018014515A1 TECHNOLOGIES FOR ADAPTIVE PROCESSING OF MULTIPLE BUFFERS 审中-公开
标题翻译：多缓冲区自适应处理技术
公开(公告)号：WO2018014515A1
公开(公告)日：2018-01-25
申请号：PCT/CN2016/114023
申请日：2016-12-31
申请人： INTEL CORPORATION , LIU, Xiaodong , DAI, Qihua , LI, Weigang , GOPAL, Vinodh
发明人： LIU, Xiaodong , DAI, Qihua , LI, Weigang , GOPAL, Vinodh
IPC分类号： G06F9/30
摘要： Technologies for adaptive processing of multiple buffers is disclosed. A compute device may establish a buffer queue to which applications can submit buffers to be processed, such as by hashing the submitted buffers. The compute device monitors the buffer queue and determines an efficient way of processing the buffer queue based on the number of buffers present. The compute device may process the buffers serially with a single processor core of the compute device or may process the buffers in parallel with single-instruction, multiple data (SIMD) instructions. The compute device may determine which method to use based on a comparison of the throughput of serially processing the buffers as compared to parallel processing the buffers, which may depend on the number of buffers in the buffer queue.
摘要翻译：公开了用于自适应处理多个缓冲器的技术。计算设备可以建立缓冲队列，应用程序可以向其提交要处理的缓冲区，例如通过散列提交的缓冲区。计算设备监视缓冲队列并基于存在的缓冲数目确定处理缓冲队列的有效方式。计算设备可以用计算设备的单个处理器核心串行处理缓冲器，或者可以用单指令多数据（SIMD）指令并行处理缓冲器。计算设备可以基于比较串行处理缓冲器的吞吐量与并行处理缓冲器的比较来确定使用哪种方法，这可以取决于缓冲器队列中的缓冲器的数量。

6. 发明申请

WO2017030600A1 INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM3 CRYPTOGRAPHIC HASHING FUNCTIONALITY 审中-公开
标题翻译：说明和逻辑提供SIMD SM3 CRYPTOGRAPHIC HASHING功能
公开(公告)号：WO2017030600A1
公开(公告)日：2017-02-23
申请号：PCT/US2015/065134
申请日：2015-12-10
申请人： INTEL CORPORATION , WOLRICH, Gilbert M. , GOPAL, Vinodh , GULLEY, Sean M. , YAP, Kirk S. , FEGHALI, Wajdi K.
发明人： WOLRICH, Gilbert M. , GOPAL, Vinodh , GULLEY, Sean M. , YAP, Kirk S. , FEGHALI, Wajdi K.
IPC分类号： H04L9/06 , H04L9/32 , G06F9/38 , G06F15/80
CPC分类号： G06F9/30145 , G06F9/30007 , G06F9/30036 , G06F21/72
摘要： Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.
摘要翻译：说明和逻辑提供SIMD SM3加密散列功能。一些实施例包括处理器，包括：解码器，用于解码SIMD SM3消息扩展的指令，指定第一和第二源数据操作数集合以及扩展范围。响应于指令的处理器执行单元从由指定扩展范围确定的第一和第二源数据操作数集执行多个SM3消息扩展，并将结果存储到SIMD目的地寄存器中。一些实施例还从中间散列值输入，源数据集和圆常数集合执行散列算法的SIMD SM3散列圆切片部分的指令。处理器执行单元在源数据集上执行一组SM3散列循环迭代，应用中间散列值输入和循环常数集合，并将新的散列值结果存储在SIMD目的寄存器中。

7. 发明申请

WO2013095547A9 APPARATUS AND METHOD OF EXECUTION UNIT FOR CALCULATING MULTIPLE ROUNDS OF A SKEIN HASHING ALGORITHM 审中-公开
标题翻译：用于计算多重环绕滑移算法的执行单元的装置和方法
公开(公告)号：WO2013095547A9
公开(公告)日：2013-09-06
申请号：PCT/US2011066988
申请日：2011-12-22
申请人： INTEL CORP , WOLRICH GILBERT M , YAP KIRK S , GUILFORD JAMES D , OZTURK ERDINC , GOPAL VINODH , FEGHALI WAJDI K , GULLEY SEAN M , DIXON MARTIN G
发明人： WOLRICH GILBERT M , YAP KIRK S , GUILFORD JAMES D , OZTURK ERDINC , GOPAL VINODH , FEGHALI WAJDI K , GULLEY SEAN M , DIXON MARTIN G
IPC分类号： G06F1/00 , G06F9/305 , G06F9/44
CPC分类号： G06F9/30029 , G06F9/30007 , G06F9/30018 , G06F9/30036 , G06F9/3885 , G06F9/3895 , H04L9/0643
摘要： An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows. a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.
摘要翻译：描述了包括指令流水线内的执行单元的装置。执行单元具有包括a）和b）的电路的多个级，如下所述。 a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四进制字的第一输入和用于接收第二四字的第二输入; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。

8. 发明申请

WO2013095648A1 THREE INPUT OPERAND VECTOR ADD INSTRUCTION THAT DOES NOT RAISE ARITHMETIC FLAGS FOR CRYPTOGRAPHIC APPLICATIONS 审中-公开
标题翻译：三个输入操作向量添加指令，不提供用于CRYPTOAPHAPH应用的算术标记
公开(公告)号：WO2013095648A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067230
申请日：2011-12-23
申请人： INTEL CORPORATION , FEGHALI, Wajdi K. , GOPAL, Vinodh , GUILFORD, James D. , OZTURK, Erdinc , WOLRICH, Gilbert M. , YAP, Kirk S. , GULLEY, Sean M. , DIXON, Martin G.
发明人： FEGHALI, Wajdi K. , GOPAL, Vinodh , GUILFORD, James D. , OZTURK, Erdinc , WOLRICH, Gilbert M. , YAP, Kirk S. , GULLEY, Sean M. , DIXON, Martin G.
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38
CPC分类号： G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30181
摘要： A method is described that includes performing the following within an instruction execution pipeline implemented on a semiconductor chip: summing three input vector operands through execution of a single instruction; and, not raising any arithmetic flags even though a result of the summing creates more bits than circuitry designed to transport the summation is able to transport.
摘要翻译：描述了一种方法，其包括在半导体芯片上实现的指令执行流水线内执行以下操作：通过执行单个指令对三个输入向量操作数相加; 并且，即使求和的结果产生比设计用于传送求和的电路更多的位能够传输，也不会提高任何算术标记。

9. 发明申请

WO2013095615A1 BITSTREAM PROCESSING USING COALESCED BUFFERS AND DELAYED MATCHING AND ENHANCED MEMORY WRITES 审中-公开
标题翻译：使用加密缓存和延迟匹配和增强存储器写入的BITSTREAM处理
公开(公告)号：WO2013095615A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067092
申请日：2011-12-23
申请人： INTEL CORPORATION , GOPAL, Vinodh , GUILFORD, Jim, D. , FEGHALI, Wajdi, K. , KARAKOYUNLU, Deniz , OZTURK, Erdnic , DIXON, Martin , AKDEMIR, Kahraman, D. , WOLRICH, Gilbert, M.
发明人： GOPAL, Vinodh , GUILFORD, Jim, D. , FEGHALI, Wajdi, K. , KARAKOYUNLU, Deniz , OZTURK, Erdnic , DIXON, Martin , AKDEMIR, Kahraman, D. , WOLRICH, Gilbert, M.
IPC分类号： H03M7/30
CPC分类号： H04L65/607 , H03M7/30 , H03M7/3086 , H04L65/608 , H04L69/04 , H04L69/22 , H04W28/06
摘要： Methods and apparatus for processing bitstreams and byte streams. According to one aspect, bitstream data is compressed using coalesced string match tokens with delayed matching. A matcher is employed to perform search string match operations using a shortened maximum string length search criteria, resulting in generation of a token stream having data and literal data. A distance match operation is performed on sequentially adjacent tokens to determine if they contain the same distance data. If they do, the len values of the tokens are added through use of a coalesce buffer. Upon detection of a distance non-match, a final coalesced length of a matching string is calculated and output along with the prior matching distance as a coalesced token. Also disclosed is a scheme for writing variable-length tokens into a bitstream under which token data is input into a bit accumulator and written to memory (or cache to be subsequently written to memory) as each token is processed in a manner that eliminates branch mispredict operations associated with detecting whether the bit accumulator is full or close to full.
摘要翻译：用于处理比特流和字节流的方法和装置。根据一个方面，使用具有延迟匹配的合并字符串匹配令牌来压缩比特流数据。使用匹配器来执行搜索字符串匹配操作，使用缩短的最大字符串长度搜索条件，导致生成具有数据和文字数据的令牌流。对顺序相邻的令牌执行距离匹配操作，以确定它们是否包含相同的距离数据。如果这样做，令牌的len值通过使用合并缓冲区来添加。在检测到距离不匹配时，计算匹配串的最终合并长度，并将其与先前匹配距离一起作为合并令牌输出。还公开了一种用于将可变长度令牌写入比特流的方案，在该比特流中，令牌数据被输入到比特累加器中，并且以消除分支错误预测的方式将每个令牌进行处理，并将其写入存储器（或高速缓存以随后写入存储器）检测位累加器是满或接近满的操作。

10. 发明申请

WO2013006388A3 EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC 审中-公开
公开(公告)号：WO2013006388A3
公开(公告)日：2013-01-10
申请号：PCT/US2012/044735
申请日：2012-06-28
申请人： INTEL CORPORATION , RADHAKRISHNAN, Sivakumar , SCHMISSEUR, Mark A. , TAN, Sin S. , HAREN, Kenneth C. , BROWN, Thomas C. , KUMAR, Pankaj , GOPAL, Vinodh , FEGHALI, Wajdi K.
发明人： RADHAKRISHNAN, Sivakumar , SCHMISSEUR, Mark A. , TAN, Sin S. , HAREN, Kenneth C. , BROWN, Thomas C. , KUMAR, Pankaj , GOPAL, Vinodh , FEGHALI, Wajdi K.
IPC分类号： G06F11/10
摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

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