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1. 发明申请

WO1998013473A1 GENETICALLY ENGINEERED YEAST WITH MODIFIED SIGNAL PEPTIDASE COMPLEX 审中-公开
标题翻译：具有修饰信号肽复合物的遗传工程YEAST
公开(公告)号：WO1998013473A1
公开(公告)日：1998-04-02
申请号：PCT/US1997017597
申请日：1997-09-25
申请人： VANDERBILT UNIVERSITY , FANG, Hong , GREEN, Neil , VAN KAER, Luc
发明人： VANDERBILT UNIVERSITY
IPC分类号： C12N01/15
CPC分类号： C12N9/52 , C12N15/81
摘要： The present invention provides a yeast cell comprising a nucleic acid functionally encoding a eukaryotic (e.g., mammalian) protein homologue of a subunit (Sec11p, Spc1p, Spc2p and/or Spc3p) of the yeast signal peptidase complex. The yeast cell of this invention can be, for example, of the genus Saccharomyces, Schizosaccharomyces, Pichia, Hansenula, Kluyveromyces and/or Yarrowia. Furthermore, the yeast cell can lack one or more functional subunits (Sec11p, Spc1p, Spc2p and/or Spc3p) of the yeast signal peptidase complex. The present invention further provides a method for producing a protein heterologous to a yeast cell comprising expressing, in the yeast cell of this invention, a nucleic acid functionally encoding the heterologous protein under conditions which permit the expression of the nucleic acid as a precursor protein having a signal peptide and processing of the precursor protein to a signal peptide-cleaved form of the protein. A method is also provided for obtaining increased production of a protein heterologous to a yeast cell comprising expressing, in the yeast cell of this invention, a nucleic acid functionally encoding the heterologous protein under conditions which permit the expression of the nucleic acid as a precursor protein having a signal peptide and processing of the precursor protein to a signal peptide-cleaved form of the protein. Additionally provided is a method for producing a yeast cell capable of increased production of a protein heterologous to the yeast cell, comprising introducing into the yeast cell (with or without one or more functional SPC subunits) a nucleic acid which functionally encodes one or more eukaryotic protein homologues of the signal peptidase complex under conditions permitting the expression of the nucleic acid as the protein homologues.
摘要翻译：本发明提供了酵母细胞，其包含功能性编码酵母信号肽酶复合物的亚基（Sec11p，Spc1p，Spc2p和/或Spc3p）的真核（例如哺乳动物）蛋白质同源物的核酸。本发明的酵母细胞可以是例如酵母属，裂殖酵母属，毕赤酵母，汉逊酵母，克鲁维酵母属和/或耶氏酵母属。此外，酵母细胞可以缺乏酵母信号肽酶复合物的一个或多个功能性亚基（Sec11p，Spc1p，Spc2p和/或Spc3p）。本发明还提供了一种用于生产与酵母细胞异源的蛋白质的方法，包括在本发明的酵母细胞中表达在允许表达核酸作为前体蛋白的条件下功能性编码异源蛋白质的核酸，信号肽和前体蛋白与信号肽切割形式的蛋白质的加工。还提供了用于获得增加对酵母细胞异源的蛋白质产生的方法，包括在本发明的酵母细胞中表达在允许核酸作为前体蛋白表达的条件下功能编码异源蛋白质的核酸具有信号肽和将前体蛋白加工成信号肽切割形式的蛋白质。另外提供了一种用于生产能够增加与酵母细胞异源的蛋白质产生的酵母细胞的方法，包括向功能上编码一种或多种真核生物的核酸引入酵母细胞（具有或不具有一个或多个功能性SPC亚基）在允许核酸作为蛋白质同系物表达的条件下，信号肽酶复合物的蛋白质同系物。

2. 发明申请

WO2005024051A1 CELL-BASED ASSAY FOR IDENTIFYING PEPTIDASE INHIBITORS 审中-公开
标题翻译：用于鉴定肽酶抑制剂的基于细胞的测定
公开(公告)号：WO2005024051A1
公开(公告)日：2005-03-17
申请号：PCT/US2004/014586
申请日：2004-05-11
申请人： VANDERBILT UNIVERSITY , FANG, Hong , GREEN, Neil
IPC分类号： C12Q1/37
CPC分类号： C12N9/6489 , C12Q1/02 , C12Q1/37 , G01N2333/39
摘要： The present invention provides assays for the identification of inhibitors of endopeptidase toxins. The assays utilize genetically engineered yeast cells that contain a conditionally expressed endopeptidase toxin. When conditions for expression of the toxin are met, the toxin cleaves a yeast (natural or engineered) peptide product that is required for yeast survival. If the yeast is grown in the presence of a candidate substance that is an inhibitor of the toxin, the yeast survives, thereby providing a rapid and sensitive identification of the inhibitor.
摘要翻译：本发明提供了鉴定内肽酶毒素抑制剂的测定法。该测定法利用含有条件表达的内肽酶毒素的遗传工程酵母细胞。当满足毒素表达条件时，毒素切割酵母存活所需的酵母（天然或工程化）肽产物。如果酵母在存在作为毒素抑制剂的候选物质的情况下生长，则酵母存活，从而提供抑制剂的快速且敏感的鉴定。

3. 发明申请

WO1995015293A1 AN ULTRA FINE POWDER CALCIUM OXIDE, PREPARATION AND USE THEREOF 审中-公开
标题翻译：超细粉末氧化钙，其制备和使用
公开(公告)号：WO1995015293A1
公开(公告)日：1995-06-08
申请号：PCT/CN1994000097
申请日：1994-12-03
申请人： BEIJING SAN-XI CHEMICAL NEW TECHNOLOGY COMPANY , CHAI, Zhifang , ZHANG, Yuanji , MAO, Xueying , FANG, Hong
发明人： BEIJING SAN-XI CHEMICAL NEW TECHNOLOGY COMPANY
IPC分类号： C01F11/06
CPC分类号： B82Y30/00 , A61K33/08 , C01F11/06 , C01P2004/51 , C01P2004/62 , C01P2004/64
摘要： The invention provides an ultra fine powder calcium oxide, wherein the oxide has a particle size of 10 -10 m. The oxide is made from a calcium carbonate by the way of a plasma decomposition. The invention further provides a calcium - containing composition, wherein the composition has the ultra fine powder calcium oxide. The composition is usable to supply men and animals with the necessary calcium.
摘要翻译：本发明提供了一种超细粉末氧化钙，其中氧化物的粒径为10 -6 -10 -9μm。氧化物通过等离子体分解的方式由碳酸钙制成。本发明还提供一种含钙组合物，其中所述组合物具有超细粉末氧化钙。该组合物可用于向男性和动物提供必需的钙。

4. 发明授权

US08339449B2 Defect monitoring in semiconductor device fabrication 有权
标题翻译：半导体器件制造中的缺陷监测
公开(公告)号：US08339449B2
公开(公告)日：2012-12-25
申请号：US12537269
申请日：2009-08-07
申请人： Barbara Fong Chin Lim , Keng Heng Lai , Tanya Yang , Victor Seng Keong Lim , Fang Hong Gn , Liang Choo Hsia
发明人： Barbara Fong Chin Lim , Keng Heng Lai , Tanya Yang , Victor Seng Keong Lim , Fang Hong Gn , Liang Choo Hsia
IPC分类号： H04N7/18
CPC分类号： G06T7/0006 , G01N21/9501 , G06T2207/10061 , G06T2207/30148
摘要： A method of forming a device is presented. The method includes providing a substrate containing at least a partially formed device thereon. The device comprises at least one defect site. A pixilated image of the defect site is acquired, and each pixel comprises a grey level value (GLV). Surrounding noises of the defect site is eliminated. A point of the image is identified as the center of the defect. A plurality of iterations to exclude outer edge pixels surrounding the center of the defect image is performed. The defect is categorized as a killer or non-killer defect.
摘要翻译：提出了一种形成装置的方法。该方法包括提供在其上至少包含部分形成的器件的衬底。该装置包括至少一个缺陷部位。获取缺陷部位的像素化图像，并且每个像素包括灰度值（GLV）。消除了缺陷部位的周围噪声。图像的一个点被识别为缺陷的中心。执行多个迭代以排除围绕缺陷图像的中心的外边缘像素。该缺陷被归类为杀伤或非杀伤性缺陷。

5. 发明申请

US20110114949A1 TEST CHIPLETS FOR DEVICES 有权
标题翻译：设备测试芯片
公开(公告)号：US20110114949A1
公开(公告)日：2011-05-19
申请号：US12621513
申请日：2009-11-19
申请人： Victor Seng Keong LIM , Rachel Yie Fang WAI , Fang Hong GN , Liang Choo HSIA
发明人： Victor Seng Keong LIM , Rachel Yie Fang WAI , Fang Hong GN , Liang Choo HSIA
IPC分类号： H01L23/544 , H01L21/66 , G06F17/50
CPC分类号： H01L22/12
摘要： A method of forming a device is disclosed. The method includes providing a substrate on which the device is formed. It also includes forming a test cell on the substrate. The test cell includes a defect programmed into the cell to facilitate defect detection.
摘要翻译：公开了一种形成装置的方法。该方法包括提供其上形成有器件的衬底。它还包括在衬底上形成测试电池。测试单元包括编程到单元中以便于缺陷检测的缺陷。

6. 发明申请

US20080244924A1 Drying method and apparatus for use of latent heat 审中-公开
标题翻译：使用潜热的干燥方法和设备
公开(公告)号：US20080244924A1
公开(公告)日：2008-10-09
申请号：US11730590
申请日：2007-04-03
申请人： Chang-Ren Chen , Juh-Ping Chang , Huann-Ming Chou , Rong-Fang Hong , Atul Sharma
发明人： Chang-Ren Chen , Juh-Ping Chang , Huann-Ming Chou , Rong-Fang Hong , Atul Sharma
IPC分类号： F26B3/28
CPC分类号： F26B3/28 , F26B9/06 , F26B21/08 , F26B23/00 , F26B25/08
摘要： A drying method for use of latent heat includes the following steps: A. installing a heating plate and a latent heat device having wax in a dry environmental space; B. placing an article to be dried in the dry environmental space; C. absorbing outside heat energy with the heating plate for drying process; D. utilizing the latent heat device to accumulate heat energy; and E. releasing the heat energy from the latent heat device for drying process. A drying apparatus for use of latent heat includes a box, a heating plate provided on the box, and a latent heat device provided in the box. The box has an entrance and a vent. The entrance is provided with a door to seal the entrance. The latent heat device comprises wax therein to do heat exchange through for drying purpose.
摘要翻译：使用潜热的干燥方法包括以下步骤：A.在干燥环境空间中安装具有蜡的加热板和潜热装置; B.将干燥物品放在干燥的环境空间中; C.用加热板吸收外部热能干燥过程; 利用潜热装置积聚热能; 和E.从潜热装置中释放热能用于干燥过程。用于潜热的干燥装置包括：箱体，设置在箱体上的加热板和设置在箱体内的潜热装置。盒子有一个入口和一个通风口。入口设有一个门，以密封入口。潜热装置包括在其中进行热交换以用于干燥目的。

7. 发明授权

US06228718B1 Method of fabricating a self-aligned split gate of a flash memory 失效
标题翻译：制造闪存的自对准分裂门的方法
公开(公告)号：US06228718B1
公开(公告)日：2001-05-08
申请号：US09468558
申请日：1999-12-21
申请人： Chih-Jen Huang , Shih-Fang Hong
发明人： Chih-Jen Huang , Shih-Fang Hong
IPC分类号： H01L218247
CPC分类号： H01L27/11521
摘要： The present invention is a method of fabricating a self-aligned split gate of flash memory. Aligned layers are formed on predetermined source regions and predetermined drain regions in advance. Spacers are formed on the sidewalls of the aligned layers. An etching rate of the spacers is different from an etching rate of the aligned layers. Therefore, if misalignment occurs during the patterning process to form a split control gate layer, the spacers also can be left after the aligned layer is removed. The remaining spacers serves as a implant mask during the implantion for the sources and the drains formation, so that the sources and the drains are formed in the respective positions of the aligned layers by self-alignment.
摘要翻译：本发明是制造闪存的自对准分裂门的方法。对准层预先在预定的源极区域和预定的漏极区域上形成。间隔物形成在对准层的侧壁上。间隔物的蚀刻速率与对准层的蚀刻速率不同。因此，如果在形成分割控制栅极层的图案化工艺期间发生不对准，则在去除对准层之后也可以留下间隔物。剩余的间隔物在用于源和漏极形成的植入期间用作植入物掩模，使得源和漏极通过自对准形成在对准层的相应位置。

8. 发明授权

US08569127B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08569127B2
公开(公告)日：2013-10-29
申请号：US13418835
申请日：2012-03-13
申请人： Chien-Yang Chen , Chen-Hua Tsai , Shih-Fang Hong , Po-Chao Tsao , Ming-Te Wei
发明人： Chien-Yang Chen , Chen-Hua Tsai , Shih-Fang Hong , Po-Chao Tsao , Ming-Te Wei
IPC分类号： H01L21/8238 , H01L21/00
CPC分类号： H01L27/0629 , H01L21/28518 , H01L21/76814 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.
摘要翻译：对半导体装置的制造方法进行说明。提供了其上具有多晶硅电阻器的基板。在覆盖多晶硅电阻器的衬底上形成介电层。蚀刻电介质层以在多晶硅电阻器上形成接触开口，其过蚀刻到多晶硅电阻器中。在接触开口中的多晶硅电阻器上形成金属硅化物层。金属材料填充在接触开口中。去除介电层，金属材料和多晶硅电阻的一部分的一部分以露出金属硅化物层。在金属硅化物层上形成金属接触。

9. 发明申请

US20130241001A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130241001A1
公开(公告)日：2013-09-19
申请号：US13418835
申请日：2012-03-13
申请人： Chien-Yang Chen , Chen-Hua Tsai , Shih-Fang Hong , Po-Chao Tsao , Ming-Te Wei
发明人： Chien-Yang Chen , Chen-Hua Tsai , Shih-Fang Hong , Po-Chao Tsao , Ming-Te Wei
IPC分类号： H01L27/088 , H01L21/768
CPC分类号： H01L27/0629 , H01L21/28518 , H01L21/76814 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.
摘要翻译：对半导体装置的制造方法进行说明。提供了其上具有多晶硅电阻器的基板。在覆盖多晶硅电阻器的衬底上形成介电层。蚀刻电介质层以在多晶硅电阻器上形成接触开口，其过蚀刻到多晶硅电阻器中。在接触开口中的多晶硅电阻器上形成金属硅化物层。金属材料填充在接触开口中。去除介电层，金属材料和多晶硅电阻的一部分的一部分以露出金属硅化物层。在金属硅化物层上形成金属接触。

10. 发明授权

US5677238A Semiconductor contact metallization 失效
标题翻译：半导体接触金属化
公开(公告)号：US5677238A
公开(公告)日：1997-10-14
申请号：US638667
申请日：1996-04-29
申请人： Fang Hong Gn , Sekar Ramamoorthy , Lap Chan , Che-Chia Wei
发明人： Fang Hong Gn , Sekar Ramamoorthy , Lap Chan , Che-Chia Wei
IPC分类号： H01L21/285 , H01L21/768 , H01L21/283
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/76843
摘要： A method for fabricating an improved connection between active device regions in silicon, to an overlying metallization level, has been developed. The method produces contacts with superior and improved barrier integrity, which permits silicon device exposure to extended thermal process times and/or higher temperature processes without metal penetration into the silicon contact junction regions. The critical element is the addition of a conformal CVD tungsten layer in the multilayer barrier structure.
摘要翻译：已经开发了用于制造硅中的有源器件区域与覆盖金属化水平之间的改进连接的方法。该方法产生具有优异和改善的屏障完整性的触点，其允许硅器件暴露于延长的热处理时间和/或较高温度过程，而不会金属渗入硅接触接合区域。关键元素是在多层阻挡结构中添加共形CVD钨层。

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