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1. 发明授权

US08691099B2 Process for fabricating MEMS devices 有权
标题翻译：制造MEMS器件的工艺
公开(公告)号：US08691099B2
公开(公告)日：2014-04-08
申请号：US12930840
申请日：2011-01-18
申请人： John Gritters , Ezekiel John Joseph Kruglick , Mathew Last
发明人： John Gritters , Ezekiel John Joseph Kruglick , Mathew Last
IPC分类号： C23F1/00
CPC分类号： G02B26/0841 , B81B2201/025 , B81B2201/042 , B81B2203/0136 , B81B2203/058 , B81C1/00182 , G02B26/101 , H02N1/006
摘要： A process for fabricating a MEMS device with movable comb teeth and stationary comb teeth. A single mask is used to define, during a series of processing steps, the location and width of both movable comb teeth and stationary comb teeth so as to assure self alignment of the comb teeth. MEMS devices are fabricated from a single multi-layer semi-conductor structure of semiconductor material and insulator material. In a preferred embodiment the process is employed to provide a MEMS mirror device having a movable structure, a movable frame, a first set of two torsional members, a first set of at least four comb drives, an outer fixed frame structure, a second set of two torsional members, and a second set of at least four comb drives.
摘要翻译：一种用于制造具有可移动梳齿和固定梳齿的MEMS装置的方法。在一系列处理步骤中，使用单个掩模来限定可移动梳齿和固定梳齿的位置和宽度，以确保梳齿的自对准。 MEMS器件由半导体材料和绝缘体材料的单个多层半导体结构制成。在优选实施例中，该方法用于提供具有可移动结构的MEMS反射镜装置，可移动框架，第一组两个扭转构件，第一组至少四个梳状驱动器，外部固定框架结构，第二组的两个扭转构件，以及第二组至少四个梳齿驱动器。

2. 发明申请

US20110093733A1 Power Channel Monitor For A Multicore Processor 有权
标题翻译：多核处理器的电源通道监视器
公开(公告)号：US20110093733A1
公开(公告)日：2011-04-21
申请号：US12582301
申请日：2009-10-20
申请人： Ezekiel John Joseph Kruglick
发明人： Ezekiel John Joseph Kruglick
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152
摘要： Technologies are generally described for power channel monitoring in multicore processors. A power management system can be configured to monitor the power channels supplying individual cores within a multicore processor. A power channel monitor can provide a direct measurement of power consumption for each core. The power consumption of individual cores can indicate which cores are encountering higher or lower usage. The usage determination can be made without sending any data messages to, or from, the cores being measured. The determined usage load being serviced by each processor core may be used to adjust power and/or clock signals supplied to the cores.
摘要翻译：技术通常用于多核处理器中的功率通道监控。电源管理系统可以配置为监视在多核处理器内提供各个内核的电源通道。电源通道监视器可以直接测量每个内核的功耗。单个内核的功耗可以指示哪些核心遇到更高或更低的使用。可以进行使用确定，而不向所测量的核心发送任何数据消息。由每个处理器核心服务的确定的使用负载可以用于调整提供给核的功率和/或时钟信号。

3. 发明申请

US20110087815A1 Interrupt Masking for Multi-Core Processors 有权
标题翻译：多核处理器的中断屏蔽
公开(公告)号：US20110087815A1
公开(公告)日：2011-04-14
申请号：US12578270
申请日：2009-10-13
申请人： Ezekiel John Joseph Kruglick
发明人： Ezekiel John Joseph Kruglick
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Technologies are generally described herein for handling interrupts within a multi-core processor. A core specific interrupt mask (“CIM”) can be adapted to influence the assignment of interrupts to particular processor cores in the multi-core processor. Available processor cores can be identified by evaluating the CIM. An interrupt with an interrupt service routine (“ISR”) that is received by the multi-core processor can be assigned to one or more of the available processor cores identified by the CIM.
摘要翻译：这里通常描述了用于处理多核处理器内的中断的技术。核心特定中断掩码（“CIM”）可以适应于影响多核处理器中特定处理器内核的中断分配。可以通过评估CIM来识别可用的处理器内核。可以将由多核处理器接收的具有中断服务程序（“ISR”）的中断分配给由CIM标识的一个或多个可用处理器内核。

4. 发明授权

US08627300B2 Parallel dynamic optimization 有权
标题翻译：并行动态优化
公开(公告)号：US08627300B2
公开(公告)日：2014-01-07
申请号：US12578295
申请日：2009-10-13
申请人： Ezekiel John Joseph Kruglick
发明人： Ezekiel John Joseph Kruglick
IPC分类号： G06F9/45
CPC分类号： G06F8/45 , G06F8/443 , G06F9/45525
摘要： Technologies are generally described for parallel dynamic optimization using multicore processors. A runtime compiler may be adapted to generate multiple instances of executable code from a portable intermediate software module. The various instances of executable code may be generated with variations of optimization parameters such that the code instances each express different optimization attempts. A multicore processor may be leveraged to simultaneously execute some, or all, of the various code instances. Preferred optimization parameters may be determined from the executable code instances that may correctly complete in the least time, or may use the least amount of memory, or that may prove superior according to some other fitness metric. Preferred optimization parameters may be used to seed future optimization attempts. Output generated from the preferred instances may be used as soon as the first instance correctly completes block.
摘要翻译：通常使用多核处理器对技术进行并行动态优化。运行时编译器可以适于从便携式中间软件模块生成可执行代码的多个实例。可以使用优化参数的变化来生成可执行代码的各种实例，使得代码实例各自表示不同的优化尝试。可以利用多核处理器来同时执行各种代码实例中的一些或全部。可以从可以在最短时间内正确完成的可执行代码实例来确定优选的优化参数，或者可以使用最少量的存储器，或者根据某些其他适合度量可以证明是优越的。优选的优化参数可用于种子未来的优化尝试。只要第一个实例正确完成块，可以使用从优选实例生成的输出。

5. 发明授权

US08234431B2 Interrupt masking for multi-core processors 有权
标题翻译：多核处理器的中断屏蔽
公开(公告)号：US08234431B2
公开(公告)日：2012-07-31
申请号：US12578270
申请日：2009-10-13
申请人： Ezekiel John Joseph Kruglick
发明人： Ezekiel John Joseph Kruglick
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Technologies are generally described herein for handling interrupts within a multi-core processor. A core specific interrupt mask (“CIM”) can be adapted to influence the assignment of interrupts to particular processor cores in the multi-core processor. Available processor cores can be identified by evaluating the CIM. An interrupt with an interrupt service routine (“ISR”) that is received by the multi-core processor can be assigned to one or more of the available processor cores identified by the CIM.
摘要翻译：这里通常描述了用于处理多核处理器内的中断的技术。核心特定中断掩码（“CIM”）可以适应于影响多核处理器中特定处理器内核的中断分配。可以通过评估CIM来识别可用的处理器内核。可以将由多核处理器接收的具有中断服务程序（“ISR”）的中断分配给由CIM标识的一个或多个可用处理器内核。

6. 发明授权

US06571029B1 Method for determining and implementing electrical damping coefficients 失效
标题翻译：确定和实施电阻尼系数的方法
公开(公告)号：US06571029B1
公开(公告)日：2003-05-27
申请号：US09896021
申请日：2001-06-30
申请人： Ezekiel John Joseph Kruglick , William K. Smock
发明人： Ezekiel John Joseph Kruglick , William K. Smock
IPC分类号： G02B626
CPC分类号： G02B6/3566 , G02B6/3512 , G02B6/3546 , G02B6/356 , G02B6/357 , G02B6/3572 , G02B6/358 , G02B6/359
摘要： In one implementation, a method for operating a plurality of MEMS devices including applying a magnitude of a selected actuation signal equal to a first substantially constant magnitude to an actuator to cause a movable structure to begin to accelerate from a first position to impact a motion stop at a second position. The method also includes decreasing the magnitude of the selected actuation signal in a first manner. The method further includes varying at least one of a start time and a duration of the decreasing magnitude of the selected actuation signal and observing a settling time of the movable structure in response to the step of varying. In some implementations, the method includes ascertaining a range of values for the start times and the corresponding durations for each of the plurality of MEMS devices that are capable of providing settling times of the movable structure in conformance with a predetermined specification based on the steps of varying and observing. Such an implementation can include using the ascertained range of values for each device and the selected actuation signal for determining an operating start time and a corresponding operating duration to construct an operating actuation signal capable of providing a settling time for all devices in conformance with the predetermined specification. The method also can include controlling a signal source with a programmed processor to selectively apply the operating actuation signal to the plurality of MEMS devices.
摘要翻译：在一个实施方案中，一种用于操作多个MEMS器件的方法，包括将等于第一基本上恒定的量值的所选择的致动信号的幅度施加到致动器，以使可移动结构从第一位置开始加速以撞击运动停止在第二个位置。该方法还包括以第一种方式减小所选择的致动信号的幅度。该方法还包括改变所选择的致动信号的减小幅度的开始时间和持续时间中的至少一个，并响应于变化的步骤观察可移动结构的建立时间。在一些实施方式中，该方法包括确定多个MEMS器件中的每一个的开始时间和相应持续时间的范围，其能够基于以下步骤来提供符合预定规范的可移动结构的建立时间变化和观察。这样的实现可以包括使用确定的每个设备的值的范围和所选择的致动信号来确定操作开始时间和相应的操作持续时间，以构建能够为所有设备提供稳定时间的操作致动信号，以符合预定的规范。该方法还可以包括用编程的处理器来控制信号源以选择性地将操作致动信号施加到多个MEMS器件。

7. 发明授权

US08856794B2 Multicore runtime management using process affinity graphs 有权
标题翻译：使用过程关联图的多核运行时管理
公开(公告)号：US08856794B2
公开(公告)日：2014-10-07
申请号：US12578321
申请日：2009-10-13
申请人： Ezekiel John Joseph Kruglick
发明人： Ezekiel John Joseph Kruglick
IPC分类号： G06F9/46 , G06F9/54
CPC分类号： G06F9/54
摘要： Technologies are generally described for runtime management of processes on multicore processing systems using process affinity graphs. Two or more processes may be determined to be related when the processes share interprocess messaging traffic. These related processes may be allocated to neighboring or nearby processor cores within a multicore processor using graph theory techniques as well as communication analysis techniques to evaluate interprocess communication needs. Process affinity graphs may be established to aid in determining grouping of processors and evaluating interprocess message traffic between groups of processes. The process affinity graphs may be based upon process affinity scores determined by monitoring and analyzing interprocess messaging traffic. Process affinity graphs may further inform splitting process affinity groups from one core onto two or more cores.
摘要翻译：通常使用技术来描述使用过程关联图的多核处理系统上的进程的运行时间管理。当进程共享进程间消息传递流量时，可以确定两个或多个进程相关。这些相关过程可以使用图论理论技术以及用于评估进程间通信需求的通信分析技术来分配给多核处理器内的相邻或附近的处理器核。可以建立过程关联图以帮助确定处理器的分组并且评估进程组之间的进程间消息流量。过程关联图可以基于通过监视和分析进程间消息传递流量而确定的过程亲和度得分。过程亲和度图可以进一步通知将过程亲和组从一个核分离到两个或多个核上。

8. 发明授权

US06556739B1 Electronic damping of MEMS devices using a look-up table 失效
标题翻译：使用查找表的MEMS器件的电子阻尼
公开(公告)号：US06556739B1
公开(公告)日：2003-04-29
申请号：US09896022
申请日：2001-06-30
申请人： Ezekiel John Joseph Kruglick
发明人： Ezekiel John Joseph Kruglick
IPC分类号： G02B626
CPC分类号： G02B6/3566 , G02B6/3512 , G02B6/3546 , G02B6/356 , G02B6/357 , G02B6/3572 , G02B6/358 , G02B6/359
摘要： In one embodiment, a MEMS apparatus having a MEMS array including a plurality of MEMS devices is provided. In some embodiments, each of the plurality of MEMS devices includes a movable structure and a second structure. In addition, in some embodiments, a plurality of signal sources are coupled to the plurality of MEMS devices so as to be capable of supplying actuation signals for actuating the movable structure to impact the second structure. Further, in some embodiments, at least one processor is coupled to the plurality of signal sources to control the actuation signals, and is configured such that each of the plurality of MEMS devices is provided with a corresponding custom actuation signal.
摘要翻译：在一个实施例中，提供了具有包括多个MEMS器件的MEMS阵列的MEMS装置。在一些实施例中，多个MEMS装置中的每一个包括可移动结构和第二结构。此外，在一些实施例中，多个信号源耦合到多个MEMS器件，以便能够提供用于致动可移动结构以致冲击第二结构的致动信号。此外，在一些实施例中，至少一个处理器耦合到多个信号源以控制致动信号，并且被配置为使得多个MEMS器件中的每一个被提供有相应的定制致动信号。

9. 发明授权

US08635606B2 Dynamic optimization using a resource cost registry 有权
标题翻译：使用资源成本注册表进行动态优化
公开(公告)号：US08635606B2
公开(公告)日：2014-01-21
申请号：US12578336
申请日：2009-10-13
申请人： Ezekiel John Joseph Kruglick
发明人： Ezekiel John Joseph Kruglick
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： Technologies are generally described for runtime optimization adjusted dynamically according to changing costs of one or more system resources. Multicore systems may encounter dynamic variations in performance associated with the relative cost of related system resources. Furthermore, multicore systems can experience dramatic variations in resource availability and costs. A dynamic registry of system resource costs can be utilized to guide dynamic optimization. The relative scarcity of each resource can be updated dynamically within the registry of system resource costs. A runtime code generating loader and optimizer may be adapted to adjust optimization according to the resource cost registry. Information regarding system resource costs can support optimization tradeoffs based on resource cost functions.
摘要翻译：一般来说，根据一个或多个系统资源的不断变化的成本动态调整运行时优化技术。多核系统可能会遇到与相关系统资源的相对成本相关的性能的动态变化。此外，多核系统可能会在资源可用性和成本方面产生巨大变化。系统资源成本的动态注册可以用来指导动态优化。每个资源的相对稀缺性可以在系统资源成本注册表内动态更新。运行时代码生成加载器和优化器可以适于根据资源成本注册表来调整优化。有关系统资源成本的信息可以支持基于资源成本函数的优化权衡。

10. 发明申请

US20110088038A1 Multicore Runtime Management Using Process Affinity Graphs 有权
标题翻译：使用过程关联图的多核运行时管理
公开(公告)号：US20110088038A1
公开(公告)日：2011-04-14
申请号：US12578321
申请日：2009-10-13
申请人： Ezekiel John Joseph Kruglick
发明人： Ezekiel John Joseph Kruglick
IPC分类号： G06F9/46
CPC分类号： G06F9/54
摘要： Technologies are generally described for runtime management of processes on multicore processing systems using process affinity graphs. Two or more processes may be determined to be related when the processes share interprocess messaging traffic. These related processes may be allocated to neighboring or nearby processor cores within a multicore processor using graph theory techniques as well as communication analysis techniques to evaluate interprocess communication needs. Process affinity graphs may be established to aid in determining grouping of processors and evaluating interprocess message traffic between groups of processes. The process affinity graphs may be based upon process affinity scores determined by monitoring and analyzing interprocess messaging traffic. Process affinity graphs may further inform splitting process affinity groups from one core onto two or more cores.
摘要翻译：通常使用技术来描述使用过程关联图的多核处理系统上的进程的运行时间管理。当进程共享进程间消息传递流量时，可以确定两个或多个进程相关。这些相关过程可以使用图论理论技术以及用于评估进程间通信需求的通信分析技术来分配给多核处理器内的相邻或附近的处理器核。可以建立过程关联图以帮助确定处理器的分组并且评估进程组之间的进程间消息流量。过程关联图可以基于通过监视和分析进程间消息传递流量而确定的过程亲和度得分。过程亲和度图可以进一步通知将过程亲和组从一个核分离到两个或多个核上。

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