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1. 发明授权

US07751276B2 Semiconductor memory device capable of performing page mode operation 有权
标题翻译：能够执行页面模式操作的半导体存储器件
公开(公告)号：US07751276B2
公开(公告)日：2010-07-06
申请号：US12328099
申请日：2008-12-04
申请人： Eun-Suk Kang , So-Hoe Kim
发明人： Eun-Suk Kang , So-Hoe Kim
IPC分类号： G11C8/18
CPC分类号： G11C8/04 , G11C7/1018 , G11C8/18
摘要： A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit of the start address and after the first clock signal is generated, and an address controller adapted to sequentially increment the start address in response to a transition of the second clock signal. The address controller sequentially accesses memory cells selected by the start address and the incremented start address in response to a transition of the second clock signal.
摘要翻译：适于执行页面模式操作的半导体存储器件包括：第一地址转换检测器，其适于在检测到起始地址的转变时产生第一时钟信号;第二地址转换检测器，适于在检测到较低的转换时产生第二时钟信号并且在产生第一时钟信号之后，以及地址控制器，其适于响应于第二时钟信号的转变而顺序地增加开始地址。地址控制器响应于第二时钟信号的转变，顺序地访问由起始地址和增加的开始地址选择的存储器单元。

2. 发明授权

US07477569B2 Semiconductor memory device capable of performing page mode operation 有权
标题翻译：能够执行页面模式操作的半导体存储器件
公开(公告)号：US07477569B2
公开(公告)日：2009-01-13
申请号：US11316897
申请日：2005-12-27
申请人： Eun-Suk Kang , So-Hoe Kim
发明人： Eun-Suk Kang , So-Hoe Kim
IPC分类号： G11C8/18
CPC分类号： G11C8/04 , G11C7/1018 , G11C8/18
摘要： A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit of the start address and after the first clock signal is generated, and an address controller adapted to sequentially increment the start address in response to a transition of the second clock signal. The address controller sequentially accesses memory cells selected by the start address and the incremented start address in response to a transition of the second clock signal.
摘要翻译：适于执行页面模式操作的半导体存储器件包括：第一地址转换检测器，其适于在检测到起始地址的转变时产生第一时钟信号;第二地址转换检测器，适于在检测到较低的转换时产生第二时钟信号并且在产生第一时钟信号之后，以及地址控制器，其适于响应于第二时钟信号的转变而顺序地增加开始地址。地址控制器响应于第二时钟信号的转变，顺序地访问由起始地址和增加的开始地址选择的存储器单元。

3. 发明申请

US20080141100A1 Semiconductor memory device having single-level cells and multi-level cells and method of driving the semiconductor memory device 失效
标题翻译：具有单级单元和多电平单元的半导体存储器件以及驱动半导体存储器件的方法
公开(公告)号：US20080141100A1
公开(公告)日：2008-06-12
申请号：US11891991
申请日：2007-08-14
申请人： Eun-suk Kang , Young-joon Choi , Sang-kil Lee , Dae-hyun Lee
发明人： Eun-suk Kang , Young-joon Choi , Sang-kil Lee , Dae-hyun Lee
IPC分类号： G11C29/00
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C29/00 , G11C2029/0409 , G11C2211/5641
摘要： A semiconductor memory device that performs an error control operation when an error exists in an externally received command or an externally received address, and a method of driving the semiconductor memory device are provided. The semiconductor memory device includes a memory cell array having a single-level cell area and a multi-level cell area, a command decoder which receives a command from an external source and decoding the command, an area determination unit which receives an address from an external source and determines whether a memory cell corresponding to the address belongs to either the single-level cell area or the multi-level cell area, a command flag generation unit which generates at least one enable control signal according to the decoded command and the determination result, and a logic circuit which generates a control signal for driving the memory cells included in the memory cell array or performs an error control operation, in response to the enable control signal.
摘要翻译：提供了当外部接收的命令或外部接收的地址存在错误时执行错误控制操作的半导体存储器件，以及驱动半导体存储器件的方法。半导体存储器件包括具有单级单元区域和多级单元区域的存储单元阵列，从外部源接收命令并解码该命令的命令解码器，从外部源，并且确定与该地址相对应的存储单元是否属于单级单元区域或多级单元区域，命令标志生成单元，其根据解码命令和确定生成至少一个使能控制信号结果以及响应于使能控制信号产生用于驱动包括在存储单元阵列中的存储单元的控制信号或执行错误控制操作的逻辑电路。

4. 发明授权

US07689741B2 Dual buffer memory system for reducing data transmission time and control method thereof 有权
标题翻译：双缓冲存储器系统，用于减少数据传输时间及其控制方法
公开(公告)号：US07689741B2
公开(公告)日：2010-03-30
申请号：US10940038
申请日：2004-09-13
申请人： Eun-Suk Kang , Jin-Yub Lee
发明人： Eun-Suk Kang , Jin-Yub Lee
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： G11C7/1075
摘要： A dual buffer memory system capable of improving system performance by reducing a data transmission time and a control method thereof are provided. The dual buffer memory system includes a flash memory block and a plurality of buffers. The dual buffer memory system uses a dual buffering scheme in which one buffer among the plurality of buffers interacts with the flash memory block and simultaneously a different buffer among the plurality of buffers interacts with a host. Therefore, it is possible to reduce a data transmission time between the flash memory and the host, thereby improving system performance.
摘要翻译：提供了能够通过减少数据传输时间来提高系统性能的双缓冲存储器系统及其控制方法。双缓冲存储器系统包括闪存块和多个缓冲器。双缓冲存储器系统使用双缓冲方案，其中多个缓冲器中的一个缓冲器与闪存块交互，并且同时多个缓冲器中的不同缓冲器与主机交互。因此，可以减少闪存与主机之间的数据传输时间，从而提高系统性能。

5. 发明授权

US07885141B2 Non-volatile memory device and method for setting configuration information thereof 有权
标题翻译：非易失性存储装置及其配置信息的设定方法
公开(公告)号：US07885141B2
公开(公告)日：2011-02-08
申请号：US11636325
申请日：2006-12-08
申请人： Eun-suk Kang
发明人： Eun-suk Kang
IPC分类号： G11C7/10
CPC分类号： G11C16/20 , G11C11/5621 , G11C2211/5641
摘要： Provided are a nonvolatile memory device and a method for setting configuration information of the nonvolatile memory device. The nonvolatile memory device can include a nonvolatile memory cell array, a configuration register and a configuration controller. The configuration controller can be configured to set configuration information in the configuration register based on the state of a select flag stored in the nonvolatile memory cell array. The nonvolatile memory device can be configured to maintain the configuration information using the select flag and a lock flag to prevent the configuration information from changing when security is utilized and reduce the likelihood of the nonvolatile memory device operating erroneously.
摘要翻译：提供一种用于设置非易失性存储器件的配置信息的非易失性存储器件和方法。非易失性存储器件可以包括非易失性存储单元阵列，配置寄存器和配置控制器。配置控制器可以被配置为基于存储在非易失性存储单元阵列中的选择标志的状态来将配置信息设置在配置寄存器中。非易失性存储器件可以被配置为使用选择标志和锁定标志来维护配置信息，以防止在使用安全性时配置信息改变，并且减少非易失性存储器件错误地操作的可能性。

6. 发明申请

US20070028037A1 MEMORY SYSTEM WITH AUTOMATIC DUAL-BUFFERING 审中-公开
标题翻译：具有自动双缓冲功能的存储器系统
公开(公告)号：US20070028037A1
公开(公告)日：2007-02-01
申请号：US11383162
申请日：2006-05-12
申请人： Eun-Suk KANG
发明人： Eun-Suk KANG
IPC分类号： G06F13/00
CPC分类号： G11C16/10 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087
摘要： A memory device having a dual buffering scheme between a host and a memory core may include an address generator to automatically generate first and second addresses in response to an initial buffer-sector address. The host may access the dual buffer in response to the first address, while the memory core may simultaneously access the dual buffer in response to the second address.
摘要翻译：具有在主机和存储器核心之间的双缓冲方案的存储器件可以包括地址发生器，以响应于初始缓冲器扇区地址来自动生成第一和第二地址。主机可以响应于第一地址访问双缓冲器，而存储器核可以响应于第二地址同时访问双缓冲器。

7. 发明授权

US07698615B2 Semiconductor memory device having single-level cells and multi-level cells and method of driving the semiconductor memory device 失效
标题翻译：具有单级单元和多电平单元的半导体存储器件以及驱动半导体存储器件的方法
公开(公告)号：US07698615B2
公开(公告)日：2010-04-13
申请号：US11891991
申请日：2007-08-14
申请人： Eun-suk Kang , Young-joon Choi , Sang-kil Lee , Dae-hyun Lee
发明人： Eun-suk Kang , Young-joon Choi , Sang-kil Lee , Dae-hyun Lee
IPC分类号： H03M13/00
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C29/00 , G11C2029/0409 , G11C2211/5641
摘要： A semiconductor memory device that performs an error control operation when an error exists in an externally received command or an externally received address, and a method of driving the semiconductor memory device are provided. The semiconductor memory device includes a memory cell array having a single-level cell area and a multi-level cell area, a command decoder which receives a command from an external source and decoding the command, an area determination unit which receives an address from an external source and determines whether a memory cell corresponding to the address belongs to either the single-level cell area or the multi-level cell area, a command flag generation unit which generates at least one enable control signal according to the decoded command and the determination result, and a logic circuit which generates a control signal for driving the memory cells included in the memory cell array or performs an error control operation, in response to the enable control signal.
摘要翻译：提供了当外部接收的命令或外部接收的地址存在错误时执行错误控制操作的半导体存储器件，以及驱动半导体存储器件的方法。半导体存储器件包括具有单级单元区域和多级单元区域的存储单元阵列，从外部源接收命令并解码该命令的命令解码器，从外部源，并且确定与该地址相对应的存储单元是否属于单级单元区域或多级单元区域，命令标志生成单元，其根据解码命令和确定生成至少一个使能控制信号结果以及响应于使能控制信号产生用于驱动包括在存储单元阵列中的存储单元的控制信号或执行错误控制操作的逻辑电路。

8. 发明申请

US20090086566A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PERFORMING PAGE MODE OPERATION 有权
标题翻译：可执行页面模式操作的半导体存储器件
公开(公告)号：US20090086566A1
公开(公告)日：2009-04-02
申请号：US12328099
申请日：2008-12-04
申请人： Eun-Suk KANG , So-Hoe KIM
发明人： Eun-Suk KANG , So-Hoe KIM
IPC分类号： G11C8/18
CPC分类号： G11C8/04 , G11C7/1018 , G11C8/18
摘要： A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit of the start address and after the first clock signal is generated, and an address controller adapted to sequentially increment the start address in response to a transition of the second clock signal. The address controller sequentially accesses memory cells selected by the start address and the incremented start address in response to a transition of the second clock signal.
摘要翻译：适于执行页面模式操作的半导体存储器件包括：第一地址转换检测器，其适于在检测到起始地址的转变时产生第一时钟信号;第二地址转换检测器，适于在检测到较低的转换时产生第二时钟信号并且在产生第一时钟信号之后，以及地址控制器，其适于响应于第二时钟信号的转变而顺序地增加开始地址。地址控制器响应于第二时钟信号的转变，顺序地访问由起始地址和增加的开始地址选择的存储器单元。

9. 发明申请

US20080126735A1 Non-volatile memory device and method for setting configuration information thereof 有权
标题翻译：非易失性存储装置及其配置信息的设定方法
公开(公告)号：US20080126735A1
公开(公告)日：2008-05-29
申请号：US11636325
申请日：2006-12-08
申请人： Eun-suk Kang
发明人： Eun-suk Kang
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C11/5621 , G11C2211/5641
摘要： Provided are a nonvolatile memory device and a method for setting configuration information of the nonvolatile memory device. The nonvolatile memory device can include a nonvolatile memory cell array, a configuration register and a configuration controller. The configuration controller can be configured to set configuration information in the configuration register based on the state of a select flag stored in the nonvolatile memory cell array. The nonvolatile memory device can be configured to maintain the configuration information using the select flag and a lock flag to prevent the configuration information from changing when security is utilized and reduce the likelihood of the nonvolatile memory device operating erroneously.
摘要翻译：提供一种用于设置非易失性存储器件的配置信息的非易失性存储器件和方法。非易失性存储器件可以包括非易失性存储单元阵列，配置寄存器和配置控制器。配置控制器可以被配置为基于存储在非易失性存储单元阵列中的选择标志的状态来将配置信息设置在配置寄存器中。非易失性存储器件可以被配置为使用选择标志和锁定标志来维护配置信息，以防止在使用安全性时配置信息改变，并且减少非易失性存储器件错误地操作的可能性。

10. 发明申请

US20060164910A1 Semiconductor memory device capable of performing page mode operation 有权
公开(公告)号：US20060164910A1
公开(公告)日：2006-07-27
申请号：US11316897
申请日：2005-12-27
申请人： Eun-Suk Kang , So-Hoe Kim
发明人： Eun-Suk Kang , So-Hoe Kim
IPC分类号： G11C8/18
CPC分类号： G11C8/04 , G11C7/1018 , G11C8/18
摘要： A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit of the start address and after the first clock signal is generated, and an address controller adapted to sequentially increment the start address in response to a transition of the second clock signal. The address controller sequentially accesses memory cells selected by the start address and the incremented start address in response to a transition of the second clock signal.

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