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1. 发明申请

US20050256977A1 Integrated circuit having processor and switch capabilities 审中-公开
标题翻译：具有处理器和开关功能的集成电路
公开(公告)号：US20050256977A1
公开(公告)日：2005-11-17
申请号：US10846458
申请日：2004-05-14
申请人： Eric Dehaemer , Mark Schmisseur , Deif Atallah
发明人： Eric Dehaemer , Mark Schmisseur , Deif Atallah
IPC分类号： G06F13/16 , G06F13/40 , G06F13/14
CPC分类号： G06F13/1684 , G06F13/4022
摘要： An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a processor and a switch. The switch may include at least one port capable of being coupled to at least one external communication link. The processor may be capable of issuing a request to the switch to request that the switch block forwarding via the at least one port of a command received by the switch. The switch may be capable of issuing to an issuer of the command, in response at least in part to receipt by the switch of the command, a response indicating absence of the at least one port from the switch. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：根据一个实施例的装置可以包括集成电路。集成电路可以包括处理器和开关。交换机可以包括能够被耦合到至少一个外部通信链路的至少一个端口。处理器可以能够向交换机发出请求，以请求交换机通过至少一个端口转发由交换机接收的命令。所述交换机可以能够至少部分地向所述交换机接收到所述命令的颁发者颁发指示所述至少一个端口不存在于所述交换机的响应。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

2. 发明申请

US20070005903A1 System and method for dynamic data prefetching 有权
标题翻译：用于动态数据预取的系统和方法
公开(公告)号：US20070005903A1
公开(公告)日：2007-01-04
申请号：US11172226
申请日：2005-06-30
申请人： Victor Lau , Pak-Iung Seto , Eric DeHaemer
发明人： Victor Lau , Pak-Iung Seto , Eric DeHaemer
IPC分类号： G06F12/00
CPC分类号： G06F3/0656 , G06F3/0611 , G06F3/0674 , G06F3/0679
摘要： According to one embodiment of the invention, a method comprises measuring memory access latency for a prefetch cycle associated with a transmission of data from a memory device to a destination device such as a storage device. Hereafter, the prefetch rate is dynamically adjusted based on the measured memory access latency.
摘要翻译：根据本发明的一个实施例，一种方法包括测量与从存储设备到诸如存储设备的目的地设备的数据传输相关联的预取周期的存储器访问等待时间。此后，基于测量的存储器访问延迟动态地调整预取速率。

3. 发明申请

US20140096137A1 Processor Having Per Core and Package Level P0 Determination Functionality 有权
标题翻译：处理器具有每个核心和封装级别P0确定功能
公开(公告)号：US20140096137A1
公开(公告)日：2014-04-03
申请号：US13631831
申请日：2012-09-28
申请人： MALINI K. BHANDARU , MATTHEW M. BACE , A LEONARD BROWN , IAN M. STEINER , VIVEK GARG , ERIC DEHAEMER , Scott P. Bobholz
发明人： MALINI K. BHANDARU , MATTHEW M. BACE , A LEONARD BROWN , IAN M. STEINER , VIVEK GARG , ERIC DEHAEMER , Scott P. Bobholz
IPC分类号： G06F9/48
CPC分类号： G06F9/4881 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F11/3409 , G06F2201/865 , G06F2201/88 , Y02D10/126 , Y02D10/152 , Y02D10/171
摘要： A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.
摘要翻译：描述了一种包括处理核心和用于处理核心的多个计数器的处理器。多个计数器将对由处理核心支持的多个线程中的每个线程计数第一值和第二值。第一个值反映已经为第一个值对应的线程请求了非睡眠状态的多个周期，以及反映已经请求非睡眠状态和最高性能状态的周期数的第二个值第二个值的相应线程。第一个值的相应线程和第二个值的相应线程是相同的线程。

4. 发明申请

US20150006915A1 Apparatus And Method To Implement Power Management Of A Processor 有权
标题翻译：实现处理器电源管理的装置和方法
公开(公告)号：US20150006915A1
公开(公告)日：2015-01-01
申请号：US13928724
申请日：2013-06-27
申请人： BASKARAN GANESAN , ERIC DEHAEMER , VINOD AMBROSE , HARJINDER HULLON , JOSEPH DOUCETTE , SEOW FUNG OOI , MIN HUANG , ZHIGUO WANG , YIN-LUNG LU , WILLIAM JOHNSON BOWHILL
发明人： BASKARAN GANESAN , ERIC DEHAEMER , VINOD AMBROSE , HARJINDER HULLON , JOSEPH DOUCETTE , SEOW FUNG OOI , MIN HUANG , ZHIGUO WANG , YIN-LUNG LU , WILLIAM JOHNSON BOWHILL
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括分组为多个群集的多个核心。基于在多个频率中的每一个处的每个核心的对应的工作电压来形成簇。每个集群包括唯一的一组核心，并且至少一个集群包括至少两个内核。所述处理器还包括功率控制单元（PCU），其响应于对第一集群的第一核心的频率变化请求而包括频率/电压控制逻辑，以从第一集群电压 - 频率（ VF）表与第一个集群关联。第一簇V-F表在第一簇的核的多个操作频率的每一个上唯一地指定对应的工作电压。描述和要求保护其他实施例。

5. 发明申请

US20140337646A1 Adaptively Limiting A Maximum Operating Frequency In A Multicore Processor 有权
标题翻译：自适应地限制多核处理器中的最大工作频率
公开(公告)号：US20140337646A1
公开(公告)日：2014-11-13
申请号：US13889785
申请日：2013-05-08
申请人： ANKUSH VARMA , IAN STEINER , AVINASH ANANTHAKRISHNAN , KRISHNAKANTH SISTLA , CHRIS POIRIER , MATTHEW BACE , ERIC DEHAEMER
发明人： ANKUSH VARMA , IAN STEINER , AVINASH ANANTHAKRISHNAN , KRISHNAKANTH SISTLA , CHRIS POIRIER , MATTHEW BACE , ERIC DEHAEMER
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3206 , Y02D10/126
摘要： In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括各自独立地执行指令的多个核心以及耦合到多个核心的功率控制单元以控制处理器的功率消耗，其中功率控制单元包括控制逻辑以减少最大操作如果在第一时间段内发生第一数量的强制执行状态转换或在第二时间段内发生第二数量的强制执行状态转换，则处理器的频率。描述和要求保护其他实施例。

6. 发明申请

US20070011548A1 Centralized error signaling and logging 有权
标题翻译：集中错误信号和记录
公开(公告)号：US20070011548A1
公开(公告)日：2007-01-11
申请号：US11165725
申请日：2005-06-24
申请人： Suresh Chemudupati , Victor Lau , Bruno DiPlacido , Eric DeHaemer
发明人： Suresh Chemudupati , Victor Lau , Bruno DiPlacido , Eric DeHaemer
IPC分类号： H04L1/00 , G06F11/00 , H03M13/00 , G08C25/00 , G06F11/30
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0781
摘要： A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.
摘要翻译：公开了一种装置，方法和系统。在一个实施例中，设备包括一个或多个错误接收单元，每个错误接收单元可操作以从协议中的给定层接收错误请求，并将接收到的错误请求同步到所有层的公共时钟域，并且仲裁器单元可操作以接收来自一个或多个错误接收单元的同步错误请求，将错误请求编码到公共错误互连上，并将编码的错误请求跨越互连路由到配置空间。

7. 发明申请

US20060271718A1 Method of preventing error propagation in a PCI / PCI-X / PCI express link 审中-公开
标题翻译：防止PCI / PCI-X / PCI快速链路中的错误传播的方法
公开(公告)号：US20060271718A1
公开(公告)日：2006-11-30
申请号：US11139222
申请日：2005-05-27
申请人： Bruno DiPlacido , Joseph Murray , Victor Lau , Marc Goldschmidt , Eric DeHaemer
发明人： Bruno DiPlacido , Joseph Murray , Victor Lau , Marc Goldschmidt , Eric DeHaemer
IPC分类号： G06F13/24
CPC分类号： G06F11/0745 , G06F11/0766 , G06F11/0793
摘要： An embodiment is a method and apparatus to prevent the propagation of an error in a transmission from an I/O processor of a peripheral device to a host in a computer system utilizing a PCI, PCI-X, or PCI Express link. An embodiment detects an error in a transmission, may shut down the transmission path, and further intercepts the confirmation message before the confirmation message can be sent to the host
摘要翻译：一个实施例是一种防止传输中的错误从外设设备的I / O处理器传播到使用PCI，PCI-X或PCI Express链路的计算机系统中的主机的方法和装置。实施例检测到传输中的错误，可以关闭传输路径，并且在确认消息可以被发送到主机之前进一步拦截确认消息

8. 发明申请

US20060123137A1 Integrated circuit having processor and switch capabilities 有权
公开(公告)号：US20060123137A1
公开(公告)日：2006-06-08
申请号：US11003319
申请日：2004-12-03
申请人： Eric DeHaemer , Deif Atallah
发明人： Eric DeHaemer , Deif Atallah
IPC分类号： G06F3/00
CPC分类号： G06F13/4022
摘要： An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a processor and a switch. The switch may comprise one or more ports capable of being coupled to one or more segments external to the switch. The processor may be capable of issuing to the switch one or more commands indicating, at least in part, one or more protocols via which the one or more ports are to communicate and/or one or more forwarding characteristics of the switch. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

9. 发明申请

US20050270988A1 Mechanism of dynamic upstream port selection in a PCI express switch 审中-公开
标题翻译： PCI Express交换机动态上行端口选择机制
公开(公告)号：US20050270988A1
公开(公告)日：2005-12-08
申请号：US10861169
申请日：2004-06-04
申请人： Eric DeHaemer
发明人： Eric DeHaemer
IPC分类号： H04J3/24 , H04L5/18
CPC分类号： H04L5/18
摘要： A PCI Express switch with ports defined to begin operation as upstream ports, and configured to perform a link training that determines when one port is connected to an upstream device and directs the other ports to operate as downstream ports.
摘要翻译：具有端口定义为开始作为上行端口的端口的PCI Express交换机，并且被配置为执行链路训练，其确定何时一个端口连接到上游设备并且引导其他端口用作下游端口。

10. 发明授权

US07657724B1 Addressing device resources in variable page size environments 失效
标题翻译：在可变页大小的环境中寻址设备资源
公开(公告)号：US07657724B1
公开(公告)日：2010-02-02
申请号：US11638222
申请日：2006-12-13
申请人： Eric DeHaemer
发明人： Eric DeHaemer
IPC分类号： G06F12/00
CPC分类号： G06F12/04
摘要： Methods and apparatus to improve addressing of device resources in variable page size environments are described. In one embodiment, an address conversion logic (which may be provided within a chipset in an embodiment) may convert a first address into a second address based on a difference between a first memory page size and the second memory page size. Other embodiments are also disclosed.
摘要翻译：描述了改善可变页大小环境中设备资源寻址的方法和设备。在一个实施例中，地址转换逻辑（在实施例中可以在芯片组内提供）可以基于第一存储器页面大小和第二存储器页面大小之间的差异将第一地址转换为第二地址。还公开了其他实施例。

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