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1. 发明授权

US5770892A Field effect device with polycrystalline silicon channel 失效
标题翻译：具多晶硅通道的场效应器件
公开(公告)号：US5770892A
公开(公告)日：1998-06-23
申请号：US460494
申请日：1995-06-02
申请人： Tsiu C. Chan , Yu-Pin Han , Elmer H. Guritz
发明人： Tsiu C. Chan , Yu-Pin Han , Elmer H. Guritz
IPC分类号： H01L21/02 , H01L21/8244 , H01L27/06 , H01L27/11
CPC分类号： H01L28/20 , H01L27/0605 , H01L27/11 , H01L27/1104 , H01L27/1108
摘要： A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active region in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.
摘要翻译： CMOS SRAM单元在作为数据存储节点的公共节点和电源之间具有多晶硅信号线。在该多晶硅信号线内制造场效应器件。场效应器件的沟道通过薄栅极介质与衬底中的有源区域分离，衬底内的有源区域用作场效应器件的控制栅极。这种器件可用于提供用于CMOS SRAM单元的多晶硅P沟道晶体管。

2. 发明授权

US06717910B1 Method and apparatus for controlling network data congestion 有权
公开(公告)号：US06717910B1
公开(公告)日：2004-04-06
申请号：US09163819
申请日：1998-09-30
申请人： Christian D. Kasper , Elmer H. Guritz
发明人： Christian D. Kasper , Elmer H. Guritz
IPC分类号： G06F1100
CPC分类号： H04L47/30 , H04L47/10 , H04L47/12 , H04L49/90 , H04L49/9068 , H04L49/9078
摘要： A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion, such as in the receive port of an HDLC controller is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

3. 发明授权

US5821136A Inverted field-effect device with polycrystalline silicon/germanium channel 失效
标题翻译：具多晶硅/锗通道的反相场效应器件
公开(公告)号：US5821136A
公开(公告)日：1998-10-13
申请号：US698129
申请日：1996-08-15
申请人： Tsiu Chiu Chan , Yu-Pin Han , Elmer H. Guritz , Richard A. Blanchard
发明人： Tsiu Chiu Chan , Yu-Pin Han , Elmer H. Guritz , Richard A. Blanchard
IPC分类号： H01L21/8244 , H01L27/06 , H01L27/092 , H01L27/11 , H01L21/00 , H01L21/84
CPC分类号： H01L27/11 , H01L27/0605 , H01L27/0922 , H01L27/1104 , H01L27/1108 , Y10S257/903 , Y10S438/981
摘要： A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices have different gate oxide layers, so the thicknesses can be independently optimized. The drain underlap of the inverted device is defined by a patterning step, so it can be increased for high-voltage operation if desired.
摘要翻译：一种CMOS器件架构，包括基板门控反相PMOS晶体管，以及体NMOS。反向PMOS沟道形成在与NMOS栅极不同的层中，并且这些层甚至可以具有不同的组成。此外，NMOS和反向PMOS器件具有不同的栅极氧化物层，因此可以独立优化厚度。倒置器件的漏极叠层由图案化步骤限定，因此如果需要，可以增加高压操作。

4. 发明授权

US5623438A Virtual ground read only memory circuit 失效
标题翻译：虚拟接地只读存储器电路
公开(公告)号：US5623438A
公开(公告)日：1997-04-22
申请号：US697482
申请日：1996-08-26
申请人： Elmer H. Guritz , Tsiu C. Chan
发明人： Elmer H. Guritz , Tsiu C. Chan
IPC分类号： G11C17/12 , H01L27/112 , G11C7/00 , H01L21/8246
CPC分类号： G11C17/12 , G11C17/126 , H01L27/112
摘要： A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.
摘要翻译：半导体只读存储器件包括以行和列为矩阵排列的存储器单元; 跨越矩阵的字线，其中一个字线连接到每行存储器单元; 并且位线与列线相互指向并且定位成使得存储器单元的每列位于位线和列线之间。矩阵被细分为单元，其中每个单元具有四个存储单元，其对称地排列成两列和两列的位线。所有四个单元在公共电节点处连接到位线，其中所选择的单元连接到列线。存储装置还包括用于选择单行中的存储单元的行选择驱动器; 用于选择单列行的列选择驱动程序; 以及用于选择与列线相邻的位线之一的电路。

5. 发明授权

US07072294B2 Method and apparatus for controlling network data congestion 有权
标题翻译：控制网络数据拥塞的方法和装置
公开(公告)号：US07072294B2
公开(公告)日：2006-07-04
申请号：US10785372
申请日：2004-02-24
申请人： Christian D. Kasper , Elmer H. Guritz
发明人： Christian D. Kasper , Elmer H. Guritz
IPC分类号： H04J1/16
CPC分类号： H04L47/30 , H04L47/10 , H04L47/12 , H04L49/90 , H04L49/9068 , H04L49/9078
摘要： A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.
摘要翻译：公开了一种用于控制以帧布置并最小化拥塞的网络数据流的方法，装置和网络设备。在接收FIFO存储器内产生指示接收FIFO存储器内的帧溢出的状态错误指示符。响应于状态错误指示器，向主处理器产生指示在接收FIFO存储器内发生帧溢出的早期拥塞中断。通过增加直接存储器访问（DMA）单元突发大小的字数或修改其他活动进程的时间片之一，丢弃输入帧并接收帧的服务增强。

6. 发明授权

US5801396A Inverted field-effect device with polycrystalline silicon/germanium channel 失效
公开(公告)号：US5801396A
公开(公告)日：1998-09-01
申请号：US488398
申请日：1995-06-07
申请人： Tsiu Chiu Chan , Yu-Pin Han , Elmer H. Guritz , Richard A. Blanchard
发明人： Tsiu Chiu Chan , Yu-Pin Han , Elmer H. Guritz , Richard A. Blanchard
IPC分类号： H01L21/8244 , H01L27/06 , H01L27/092 , H01L27/11 , H01L29/04
CPC分类号： H01L27/11 , H01L27/0605 , H01L27/0922 , H01L27/1104 , H01L27/1108 , Y10S257/903 , Y10S438/981
摘要： A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices have different gate oxide layers, so the thicknesses can be independently optimized. The drain underlap of the inverted device is defined by a patterning step, so it can be increased for high-voltage operation if desired.

7. 发明授权

US5377153A Virtual ground read only memory circuit 失效
标题翻译：虚拟接地只读存储器电路
公开(公告)号：US5377153A
公开(公告)日：1994-12-27
申请号：US982988
申请日：1992-11-30
申请人： Elmer H. Guritz , Tsiu C. Chan
发明人： Elmer H. Guritz , Tsiu C. Chan
IPC分类号： G11C17/12 , H01L27/112 , G11C7/00 , G11C11/00
CPC分类号： G11C17/12 , G11C17/126 , H01L27/112
摘要： A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.
摘要翻译：半导体只读存储器件包括以行和列为矩阵排列的存储器单元; 跨越矩阵的字线，其中一个字线连接到每行存储器单元; 并且位线与列线相互指向并且定位成使得存储器单元的每列位于位线和列线之间。矩阵被细分为单元，其中每个单元具有四个存储单元，其对称地排列成两列和两列的位线。所有四个单元在公共电节点处连接到位线，其中所选择的单元连接到列线。存储装置还包括用于选择单行中的存储单元的行选择驱动器; 用于选择单列行的列选择驱动程序; 以及用于选择与列线相邻的位线之一的电路。

8. 发明授权

US5135888A Field effect device with polycrystalline silicon channel 失效
标题翻译：具多晶硅通道的场效应器件
公开(公告)号：US5135888A
公开(公告)日：1992-08-04
申请号：US531014
申请日：1990-05-31
申请人： Tsiu C. Chan , Yu-Pin Han , Elmer H. Guritz
发明人： Tsiu C. Chan , Yu-Pin Han , Elmer H. Guritz
IPC分类号： H01L21/8238 , H01L21/02 , H01L21/8244 , H01L27/06 , H01L27/092 , H01L27/11
CPC分类号： H01L27/11 , H01L27/0605 , H01L27/1104 , H01L27/1108 , H01L28/20 , H01L27/1112
摘要： A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SPRAM cells.
摘要翻译： CMOS SRAM单元在作为数据存储节点的公共节点和电源之间具有多晶硅信号线。在该多晶硅信号线内制造场效应器件。场效应器件的沟道通过薄栅电介质与衬底中的有源区域分离，并且衬底内的有源区域用作场效应器件的控制栅极。这种器件可用于提供用于CMOS SPRAM单元的多晶硅P沟道晶体管。

9. 发明授权

US4142118A Integrated circuit with power supply voltage level detection 失效
标题翻译：具有电源电压检测的集成电路
公开(公告)号：US4142118A
公开(公告)日：1979-02-27
申请号：US825602
申请日：1977-08-18
申请人： Elmer H. Guritz
发明人： Elmer H. Guritz
IPC分类号： G01R19/165 , H01L21/822 , H01L27/04 , H02J1/00 , H03K19/003 , H03K3/00
CPC分类号： G01R19/16552
摘要： An MOS integrated circuit includes internal circuitry for detecting the voltage level of an external power supply. The internal circuitry comprises networks for producing two reference voltages, each of which varies with supply voltage in a different but predictable manner such that when the reference voltages are equal, the supply voltage is at a sufficiently high level to assure the generation of valid logic levels. As the supply voltage increases beyond such level, the two reference voltages diverge in value, detection of which is achieved with a different amplifier. Circuitry responsive to the output of the differential amplifier gives a positive indication of sufficient supply voltage to other circuit portions of the integrated circuit device.
摘要翻译： MOS集成电路包括用于检测外部电源的电压电平的内部电路。内部电路包括用于产生两个参考电压的网络，每个参考电压以不同但可预测的方式随着电源电压而变化，使得当参考电压相等时，电源电压处于足够高的水平以确保生成有效的逻辑电平。随着电源电压增加超过这种电平，两个参考电压的价值发散，其检测由不同的放大器实现。响应于差分放大器的输出的电路给出了对集成电路器件的其它电路部分的足够电源电压的肯定指示。

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